A silicon retina is an intelligent vision sensor that can execute real-time image preprocessing by using a parallel analog circuit that mimics the structure of the neuronal circuits in the vertebrate retina. For enhancing the sensor's robustness to changes in illumination in a practical environment, we have designed and fabricated a silicon retina on the basis of a computational model of brightness constancy. The chip has a wide-dynamic-range and shows a constant response against changes in the illumination intensity. The photosensor in the present chip approximates logarithmic illumination-to-voltage transfer characteristics as a result of the application of a time-modulated reset voltage technique. Two types of image processing, namely, Laplacian-Gaussian-like spatial filtering and computing the frame difference, are carried out by using resistive networks and sample/hold circuits in the chip. As a result of these processings, the chip exhibits brightness constancy over a wide range of illumination. The chip is fabricated by using the 0.25- μm complementary metal-oxide semiconductor image sensor technology. The number of pixels is 64 × 64, and the power consumption is 32 mW at the frame rate of 30 fps. We show that our chip not only has a wide-dynamic-range but also shows a constant response to the changes in illumination.

To detect neural spike signals, low-power neural signal detection amplifiers must amplify small neural signals of a few hundred Hz frequency while suppressing large a DC offset voltage, a 1/f noise of MOSFETs, and an induced noise of AC power supply. To overcome the problem of unwanted noise at such a low signal level, a low-noise neural signal detection amplifier with low-frequency noise suppression scheme was developed utilizing a new autozeroing technique. A test chip was designed and fabricated with a mixed signal 0.18µm CMOS technology. The voltage gain of 36dB at the bandwidth of the neural signal and the gain reduction of 20dB at AC supply noise of 60Hz were obtained. The input equivalent noise and power dissipation were 90nV/root-Hz and 90µW at a supply voltage of 1.5V, respectively.

In this paper, we propose a simplified multi-path aggregation scheme, Ethernet with flow label for multi-path, called EFL-MP. There are several aggregation schemes, such as link aggregation and multi-path TCP, for multi-path load balancing. However, link aggregation does not distribute a single flow into multiple paths due to its MAC address based flow dispatch. In addition, the multipath TCP scheme is not suitable for implementing into hardware because of the implementation complexity caused by the management of the two stages of sequence number (SEQ) (i.e., the SEQ assigned to a path and the SEQ assigned to the flow); thus it fails to provide high throughput and short latency. To maximize data transfer throughput and minimize latency, we employed a single-stage sequence number scheme with a reorder-buffer-usage-based retransmission activating algorithm. Simulation results show that EFL-MP provides high throughput and short latency despite its simple scheme, and its throughput and its latency suit to use for interconnection transport. In addition, we demonstrate that our proposed retransmission activating algorithm activates retransmission due to packet losses earlier than the conventional timer-based retransmission activating algorithm.

This paper proposes a novel Network Address Translator (NAT) traversal technology to create Peer-to-Peer (P2P) connections through NAT devices, enabling load on the relaying server to be remarkably reduced. The conventional NAT traversal technologies can inflict heavy load on the relaying server because they cannot be applied to NAT devices which randomly assign the port number. In addition, such technologies can overload the relaying server because it must exchange packets with terminals to estimate NAT device's IP address/port number. Our technology estimates the IP address/port number without the relaying server based on a payload checksum of an ICMP message sent back after an investigating packet is transmitted toward a desired peer. Our technology can create P2P connections without inflicting load on the relaying server even in the case where NAT devices randomly assign the port number because it can exactly estimate the assigned port number with only terminal-side processing. This paper clarifies that our technology can reduce more than 80% of the load on the relaying server as compared with the conventional technologies.

We propose a method for multilayer in-service reconfiguration for network computing systems that minimizes the total service downtime. Although both software and hardware virtualization technologies has been proposed for dynamic reconfiguration, each one is currently designed to be executed independently and thus their cooperative operations that dynamically reconfigure both of them have not been well-considered. We have developed a method for multilayer in-service reconfiguration that comprises Ethernet-based distributed device reconfiguration (hardware layer), fine-granular I/O service continuity management (software layer), and their orchestration. Application to the management of a session initiation protocol server system built on distributed resources demonstrated that this method achieves dynamic load balancing in response to call rate increases without any failed calls.

In this paper, the authors propose a new remote home-access technology, SoftWire, and describe a prototype system in CCNC 2006. Current remote home-access technologies require consumers to know a NAT/Firewall (NAT/FW) IP address and to configure NAT/FW ports to traverse the NAT/FW. This configuration is particularly troublesome for consumers given that changeable IP addresses allocated by DHCP are difficult to be known in advance and the port configuration is not trivial. SoftWire can easily provide a remote home access without NAT/FW’s IP address information and any port configuration by a NAT/FW-traversing scheme based on mail-based callback access. In addition, SoftWire allows consumers to use any application by an Ethernet tunneling scheme based on Ethernet over SSL. In CCNC 2006, we demonstrate the remote home access between US and Japan using SoftWire, and show that it can provide sufficient throughput for various applications including streaming media.

Recently, a new global open Ethernet (GOE) architecture was proposed as a cost-effective scalable solution for the next generation of VPNs over an optical network infrastructure. In this paper, we present a traffic engineering design for networks that support the GOE architecture. The current extensions of the spanning tree protocol (STP), such as rapid spanning tree (RST) and multiple spanning tree (MST), use a link cost metric which is inversely proportional to the link capacity. In order to achieve a better load balancing in the network, we propose to use the link cost metric which is a function of the current link load. The traffic engineering algorithms presented in this paper use two different link cost functions. We comment on the performance of those heuristic algorithms for various network topologies and under several traffic scenarios. Our results demonstrate a significant improvement in the network utilization when the link cost metric is a function of the link load compared to the case when it is inversely proportional to the link capacity.

This paper presents an overview of global open Ethernet (GOE) architecture as a cost-effective Ethernet-based virtual private network (VPN) solution, and discusses a hardware and software implementation of a prototype system. Three main approaches have been proposed for a VPN solution on metro-area network: resilient packet ring, Ethernet over multiprotocol label switching (EoMPLS), virtual bridged local area network-tag stacking (Q-in-Q). None of these schemes can satisfy the following requirements at the same time: network topology flexibility, affordable network functionalities, low equipment cost, and low operational cost. The proposed GOE system is designed to solve VPN management problems of these approaches with MPLS VPN functionality at a low cost of Ethernet-based solution. The key components of GOE are: 1) a novel GOE tag for high-speed switching and 2) a novel routing and protection module via per-destination multiple rapid spanning tree protocol (PD-MRSTP). Via the analytical performance evaluation of EoMPLS, Q-in-Q, and GOE, we show that the memory cost and the network utilization of GOE is two-three times smaller and 22% higher than the other approaches, respectively. We also have developed a GOE prototype system and obtained the following remarkable hardware and software performance results. The GOE core switch delivered 100% of theoretical maximum throughput (10 G) with zero packet loss even with the field programmable gate array platform, and its 10-G port density is 1.5 times denser than the best currently available products. The GOE switch using PD-MRSTP also delivered a significantly fast protection switching time (1.975 ms), which was significantly faster than legacy Ethernet switches. These performance evaluation results prove that the proposed GOE system can be used as a cost-effective high-performance Ethernet-based VPN solution.

Dynamic replication schemes for cost-effective, scalable content delivery networks (CDNs) are discussed. Based on content replication granularity, current dynamic replication approaches can be classified into entire replication (entire content is replicated) and object replication (individual objects are replicated) schemes. The drawbacks of these schemes are low replication performance and low scalability, respectively. We propose two schemes delivering replication performance close to that of object replication scheme with replication granularity close to that of entire replication scheme. The schemes aggregates objects in the origin server into multiple content groups and then replicate them on per-group granularity. The content groups are either statically created in advance or dynamically created upon replication. Simulation of the proposed scheme showed that the scheme of dynamic group creation can achieve almost the same performance as the optimal scheme of object replication. Even the scheme of static group creation provides much better performance than entire replication under skewed request distribution. The effect of the number of content groups on performance is also investigated.

A Transition Controllable Noise Source (TCNS) generates substrate noises with controlled transitions in size, interstage delay, and direction. The noises are measured in a 100-ps 100-uV resolution by a linear substrate voltage detector that uses a front-end PMOS source follower probing substrate potential and a back-end latch comparator for sampling/digitizing the source follower output. A 0.4-um CMOS test chip demonstrates the effectiveness of these circuits in performing advanced researches on the substrate noise.

Adaptive and efficient multiple path pre-computation schemes for QoS routing protocols such as the QoS-enabled open shortest path first (OSPF) protocol are discussed. Conventionally, for QoS routing protocols that pre-compute multiple disjoint paths as candidate paths, both the convergence time for first bootstrapping and the update time of candidate path upon detection of a network failure are quite long, particularly in large-scale networks. We propose two schemes for efficient pre-computation of multiple paths: (i) adaptive pre-computation based on the current CPU load to reduce the convergence time for the first bootstrapping, and (ii) a virtual area partitioning (VAP) algorithm to reduce the update time of the multiple candidate paths. Simulation of the proposed schemes showed that the adaptive pre-computation significantly reduces the convergence time without degrading the optimality of routing entries. It also showed that VAP reduces the processing delay of the multiple path calculation to half that of the conventional k-shortest path (KSP) algorithm.

This paper describes a clustering algorithm for vector quantizers using a “stochastic association model”. It offers a new simple and powerful soft- max adaptation rule. The adaptation process is the same as the on-line K-means clustering method except for adding random fluctuation in the distortion error evaluation process. Simulation results demonstrate that the new algorithm can achieve efficient adaptation as high as the “neural gas” algorithm, which is reported as one of the most efficient clustering methods. It is a key to add uncorrelated random fluctuation in the simi- larity evaluation process for each reference vector. For hardware imple- mentation of this process, we propose a nanostructure, whose operation is described by a single-electron circuit. It positively uses fluctuation in quantum mechanical tunneling processes.

No abstract available.

Substrate crosstalk modeling and analysis tec hniques for a reliable SoC oriented mixed signal IC design are outlined.Substrate noise measurements b y use of a source follo w erand a latc hed comparator clearly indicate that L 1 di=dt and R 1 i eects on Vdd/Gnd wirings appear in the substrate.An experimental full chip substrate crosstalk v eri cation system based on a macroscopic substrate noise model efciently analyzes the analog performance degradation relev an t to the digital activit y on the same chip.

No abstract available.

Analog-digital merged circuit architecture using pulse modulation signals and its application to functional image sensors with parallel focal plane processing are reported. The architecture is based on switched current integration and time domain charge-to-pulse conversion techniques. Parallel analog calculations such as add/sub and multiply/add are realized with low supply voltage and low power dissipation utilizing deep-sub /spl mu/m CMOS technologies. A functional CMOS image sensor which realizes parallel PWM readout, block averaging for gray scale image data, and simple pattern detection, and calculations for x- and y-projections and centers of gravity of binary image data, is proposed. A functional image sensor test chip with 56/spl times/56 pixels was fabricated in a 6 mm/spl times/6 mm chip with a 0.8 /spl mu/m CMOS technology is described.

This paper proposes a hierarchical multilayer QoS routing system with dynamic SLA management for large-scale IP networks. Previously, the promising approach to provide QoS in large-scale IP networks using a mixture of DiffServ-based QoS management and MPLS-based traffic engineering has been actively discussed. However, the introduction of QoS exacerbates the already existing scalability problems of the standard IP routing protocols. In order to address this issue, we propose a new scalable routing framework based on hierarchical QoS-aware path computation. We augment the existing OSPF and CR-LDP protocols to support hierarchical QoS routing, QoS aggregation, and QoS reservation in our MPLS-DiffServ-based hierarchical routing network. In order to provide additional flexibility and cost-efficiency, we augment the network with a policy server which is capable of dynamically handling SLAs between the networks and providing load balancing management within the network. We implement a prototype of the proposed framework and study its performance with a virtual network simulator and specially designed QoS routing algorithm simulator. In our simulations, we evaluate both the implementation complexity and algorithms performance; the results demonstrate the efficiency of the framework and its advantages over the existing proposals.

A transition-controllable noise source is developed in a 0.1-/spl mu/m P-substrate N-well CMOS technology. This noise source can generate substrate noises with controlled transitions in size, interstage delay and direction for experimental studies on substrate noise properties in a mixed-signal integrated circuit environment. Substrate noise measurements of 100 ps, 100-/spl mu/s resolution are performed by indirect sensing that uses the threshold voltage shift in a latch comparator and by direct probing that uses a PMOS source follower. Measured waveforms indicate that peaks reflecting logic transition frequencies have a time constant that is more than ten times larger than the switching time. Analyses with equivalent circuits confirm that charge transfer between the entire parasitic capacitance in digital circuits and an external supply through parasitic impedance to supply/return paths dominates the process, and the resultant return bounce appears as the substrate noise.

We consider a large population of mobile stations that are interconnected by a multihop wireless network. The applications of this wireless infrastructure range from ad hoc networking (e.g., collaborative, distributed computing) to disaster recovery (e.g., fire, flood, earthquake), law enforcement (e.g., crowd control, search-and-rescue), and military (automated battlefield). Key characteristics of this system are the large number of users, their mobility, and the need to operate without the support of a fixed (wired or wireless) infrastructure. The last feature sets this system apart from existing cellular systems and in fact makes its design much more challenging. In this environment, we investigate routing strategies that scale well to large populations and can handle mobility. In addition, we address the need to support multimedia communications, with low latency requirements for interactive traffic and quality-of-service (QoS) support for real-time streams (voice/video). In the wireless routing area, several schemes have already been proposed and implemented (e.g., hierarchical routing, on-demand routing, etc.). We introduce two new schemes-fisheye state routing (FSR) and hierarchical state routing (HSR)-which offer some competitive advantages over the existing schemes. We compare the performance of existing and proposed schemes via simulation.

We propose a new private network-to-network interface (PNNI) aggregation algorithms for hierarchical ATM networks. Standard PNNI routing provides a scalable hierarchical routing capability to support a large ATM network, and its hierarchy mechanism can decrease the network complexity significantly. However, in order to support effective QoS-based routing across foreign subnetworks, the topology aggregation mechanism, representing the lower level network topology to higher level, becomes a key issue. PNNI specification defines general notions of this aggregation mechanism, leaving enough opportunities for subnetwork administrators to choose the amount of aggregated information that they advertise. So far, no feasible PNNI compliant algorithms have been proposed. We propose a new three step aggregation scheme to solve the problem. We evaluated the proposed scheme, based on large-scale simulations with different network topologies, traffic scenarios, and performance metrics. The proposed scheme delivers good network performance while significantly reducing the network complexity.

A high-speed programmable digital signal processor VLSI with an 18-bit floating-point architecture and a 32-bit micro-instruction has been fabricated using 1.2µm CMOS technology. The device contains 280k transistors and executes every floating-point operation within a 50ns machine-cycle. The architecture differs from that of the DSSP (Digital Speech Signal Processor), reported previously, in its high-speed parallel pipeline structure, 16k-byte on-chip micro-program ROM, floating-point ALU capable of 50ns operation, as well as in its enhanced DSP instruction set.

High resolution oversampling analog-to-digital and digital-to-analog converters are proposed. These converters utilize novel multi-stage noise shaping modulation techniques which can be implemented with fine pattern MOS technology. The modulators consist of multi-connected delta sigma modulation loops with single integration. The quantization noise in the first loop is re-quantized by the second loop. That is, the noise is canceled by adding the second loop output signals to the first loop output. The resolution of the modulators increases in proportion to the number of stages and there are no feedback-loop stability problems. An experimental prototype chip is fabricated using 1.5µm CMOS technology. This chip achieves a wide dynamic range of 88dB at a baseband of 3.4KHz and sampling rate of 2.048MHz. This dynamic range corresponds to a 14-bit equivalent resolution.

A brand-new floating-point Digital Speech Signal Processor VLSI (DSSP), intended for a wide range of applications in speech processing, is developed. For speech applications, a wide dynamic range vector operation that includes FFT and complex arithmetic is necessary in executing a highly-complicated coding algorithm that treats a large amount of windowed data collectively. To meet this requirement, the floating-point data format and hardware architecture is extensively studied. The DSSP, which is fabricated using 2.5um CMOS technology, completes almost all the floating-point operations within a 150ns machine-cycle.

This paper describes a 32kbit/s adaptive delta modulation (ADM) CODEC which can be applied to digital portable telephones. This ADM CODEC employs a new adaptation algorithm and parameters adjusted for speech signals. The encoding algorithm makes it possible to achieve higher quality with the 32 kbit/s ADM CODEC than with 6 bit µ-law PCM coding. The developed ADM CODEC including a coder, a decoder and switched-capacitor filters on a chip can operate on a single power supply(3.6∼ 5V). The power dissipation is only 30 mW during normal operation and less than 10 mW in the power-down mode. The CMOS chip is an a 16-pin package, 7 × 4.3mm.