This paper describes the design methodology used to build an experimental 1.0 GigaHertz PowerPC integer microprocessor at IBM's Austin Research Laboratory. The high frequency requirements dictated the chip composition to be almost entirely custom macros using dynamic circuit techniques. The methodology presented will cover design and verification tools as well as circuit constraints and microarchitecture philosophy. The microarchitecture, circuits and tools were defined by the high frequency requirements of the processor as well as the aggressive design schedule and size of the design team.

In this paper, we present a method for efficiently obtaining area and delay estimates from RTL descriptions of a logic design. The estimates are obtained through fast compiler-type optimizations on the RTL descriptions followed by application of best-fit polynomial area and delay models on the resulting technology-independent representation. The estimation techniques were incorporated into a tool called QUEST. QUEST was used by designers of a large commercial CPU to obtain quick feedback on the area and delay impart of behavioral modifications, resulting In significant savings in design schedule.

As devices and lines shrink into the deep submicron range, the propagation delay of signals can be effectively improved by repowering the signals using intermediate buffers placed within the routing trees. Almost no existing timing driven floorplanning and placement approaches consider the option of buffer insertion. As such, they may exclude solutions, particularly early in the design process, with smaller overall area and better routability. In this paper, we propose a new methodology in which buffered trees are used to estimate wire delay during floorplanning. Instead of treating delay as one of the objectives, as done by the majority of previous work, we formulate the problem in terms of delay bounded buffered trees (DBB-tree) and propose an efficient algorithm to construct a DBB spanning tree for use during floorplanning. Experimental results show that the algorithm is very effective. Using buffer insertion at the floorplanning stage yields significantly better solutions in terms of both chip area and total wire length.

No abstract available.

This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional speci cation.The method eciently propagates mismatched p atterns from erroneous outputs backward into the network and calculates circuit regions which most likely contain the error(s).In contrast to previous approaches, the described t e chnique does not depend on a xed set of error models.Therefore, it is more general and especially suitable for transistor-level circuits, which have a broader variety of possible design errors than gate-level implementations.Furthermore, the proposed method is also applicable for incomplete sets of mismatched p atterns and hence c an be used not only as a debugging aid for formal veri cation techniques but also for simulationbased approaches.Experiments with industrial CMOS circuits show that for most design errors the identi ed problem region is less than 3% of the overall circuit.

The benefits of early package wirability analysis to the large system design process are discussed. The authors show that preliminary design exploration coupled with appropriate prediction tools provide designers with a powerful early evaluation methodology. PEPPER, an interactive package design and performance prediction tool, is described, which allows designers to quickly analyze system and technology tradeoffs very early in the design cycle. PEPPER has been evaluated on a number of large system components and the results have been very encouraging in terms of accurately predicting package wiring characteristics as well as providing insight into package design.>