Scalable and power efficient multi-core architectures must be performance heterogeneous to accommodate semi-conductor parametric variations and non-uniform access to shared resources. Due to its rate matching, a NoC on a Voltage-Frequency Island architecture can connect cores without forcing each one to give up its own operating point for the chip-wide common worst case. With run-time adaptive routing and task-to-core mapping, a NoC can run at the average not the worst case network saturation bandwidth. These run-time processes compensate for variations because they match application resource requirements with heterogeneous cores and routers. We focus on adaptive routing that simultaneously combats communication load imbalance from on-die variations and application topology. We show that even with static, fixed task-to-core mapping on multi-core architectures affected by stochastic variations, our MATC router increases the expected saturation bandwidth by 7-25% vs Dimension Order router. With systematic variations, the improvements are 5-50%. These gains compensate for saturation bandwidth degradation due to manufacturing variations and help to reduce design guard-bands.

C-slow retiming is a process of automatically increasing the throughput of a design by enabling fine grained pipelining of problems with feedback loops. This transformation is especially appropriate when applied to FPGA designs because of the large number of available registers. To demonstrate and evaluate the benefits of C-slow retiming, we constructed an automatic tool which modifies designs targeting the Xilinx Virtex family of FPGAs. Applying our tool to three benchmarks: AES encryption, Smith/Waterman sequence matching, and the LEON 1 synthesized microprocessor core, we were able to substantially increase the total throughput. For some parameters, throughput is effectively doubled.

The SCORE compute model uses fixed-size, virtual compute and memory pages connected by stream links to capture the definition ofa computation abstracted from the detailed size ofthe physical hardware. When the number of physical compute pages is smaller than the number of virtual compute pages in the abstract computation graph, the design is time-multiplexed onto the available physical hardware. A key component ofthis strategy is an automatic scheduler that selects the temporal sequencing ofvirtual resources onto the physical device. We describe a quasistatic scheduling strategy that retains the full semantic power of the dynamic SCORE flow graph while taking advantage ofstatic scheduling techniques at program load time to hoist most ofthe computational work out of the inner scheduling loops. This strategy reduces online scheduling work per reconfiguration epoch by an order of magnitude. In addition, a more global perspective available from offline-scheduling improves schedule quality, resulting in a net reduction oftotal execution time by 46–81%. 1.