This paper proposes a novel Agile Physical Compiler (APCer) for multi-port register files based on a standard cell library. It employs a Performance, Power and Area (PPA)-driven genetic algorithm to facilitate agile iterations and design generation. APCer can automatically iterate, generate, and optimize floorplan, rapidly creating efficient register file circuits and layouts with specified capacity and port numbers. Additionally, APCer responds to user-defined PPA requirements, enabling targeted design optimizations. It accelerates the register file design duration by over 40× and 20× compared with the full custom approach and existing compilers, respectively. Compared to existing compilers, APCer improves performance by 20.7% and reduces power consumption by 33.9%. Compared to the full custom approach, APCer improves performance by 31.5% and reduces power consumption by 28.8%.

With the advancement of semiconductor technology, circuits have become increasingly susceptible to errors induced by radiation. Traditional approaches to enhancing the resilience of circuits against single-node upsets (SNUs) are insufficient to meet the robustness standards of modern designs. This article proposes a high-performance, low-power latch, named high-performance low-power double-node upset resilient latch (HLDRL), which is designed to exhibit exceptional resilience against double-node upsets (DNUs). Its design has six intricately interconnected C-elements (CEs) and two three-input CEs, for error interception, ensuring robust performance even in the case of DNUs. The Technology Computer Aided Design (TCAD) tool is used to validate the effectiveness of the HLDRL. Besides, comprehensive simulations are conducted utilizing the advanced SMIC 55-nm process technology. These simulation results show that our proposed HLDRL latch can autonomously recover from any DNU and thereby ensure the integrity of the system. Moreover, compared with existing DNU-resilient latches, the proposed HLDRL latch exhibits substantial improvements in terms of multiple metrics. On average, the proposed latch achieves an impressive 29.39% dynamic power saving, a remarkable 40.04% increase in speed, a notable 4.81% reduction in area, and a substantial 53.96% decrease in the power-delay–area product (PDAP). In the post-layout simulation, the proposed latch achieves a 30.39% dynamic power saving, a 36.47% increase in speed, and an impressive 52.38% decrease in PDAP. Furthermore, the proposed latch demonstrates enhanced resilience against variations in process, supply voltage, and temperature (PVT).

Low-energy, radiation-hardened chips play a crucial role in the application of aerospace electronic equipment. This is because aerospace chips are susceptible to soft errors caused by single event upsets (SEUs) from space particle bombardment, as well as impacts on energy efficiency. As a vital core component of chips, memory storage, its key nodes becoming more sensitive to technological advancement. Moreover, the limited energy supply of the anti-radiation chip and excessive power consumption can result in an excessive burden on the thermal control system. In this paper, a low-energy-enhanced critical charge 16TSRAM (SAW16T) is proposed. To demonstrate the relative performance of SAW16T, the state of art technologies of other radiation-hardened memory cells, such as SARP12T, RH12T, RSP14T, EDP12T, SIS10T and SUR16T, are compared. Simulations are conducted at 27 °C using a 65-nm CMOS technology with a supply voltage of 1.2V. All sensitive nodes of SAW16T are able to recover to their initial states after being affected by soft errors. The critical charge of node Q hits 300fc under typical (tt), slow (ss), and slow-N fast-P (snfp) process corners, whereas node S1's critical charge reaches 300fc in tt, fast (ff), ss, fast-N slow-P (fnsp), and snfp process corners, tripling the reference value in literature. SAW16T exhibits the shortest write access time compared to the aforementioned cells, with hold power consumption reduced by 99.9%, 49.95%, 43.8%, 21.6%, and 62.9%, compared to RH12T, RSP14T, EDP12T, SIS10T, SUR16T, respectively. Furthermore, SAW16T has been demonstrated superior performance in comprehensive performance evaluations.

As technology scales down, the critical charge (QC) of vulnerable nodes decreases, making SRAM cells more susceptible to soft errors in the aerospace industry. This article proposes a Soft-Error-Aware 16T (S8P8N) SRAM cell for aerospace applications to address this issue. The properties of S8P8N are evaluated and compared with 6T, DICE, QUCCE12T, WEQUATRO, RHBD10T, RHBD12T, S4P8N, SEA14T, and SRRD12T. Simulation results indicate that all vulnerable nodes and key node pairs of the proposed cell can recover to their original states when affected by a soft error. Additionally, it can recover from key multinode upsets. The write speed of the proposed cell is found to be reduced by 20.3%, 50.1%, 74.1%, 63.7%, and 50.41% compared to 6T, DICE, QUCCE12T, WEQUATRO, and RHBD10T, respectively. The read speed of the proposed cell is found to be reduced by 56.6%, 52.2%, 62.5%, and 35.2% compared to 6T, SRRD12T, RHBD12T, and S4P8N, respectively. It also shows that the hold power of the proposed cell is found to be reduced by 14.1%, 13.8%, 17.7%, and 23.4% compared to DICE, WEQUATRO, RHBD10T, and RHBD12T. Furthermore, the read static noise margin (RSNM) of the proposed cell is found to be enhanced by 157%, 67%, and 32% compared to RHBD12T, SEA14T, and SRRD12T. All these improvements are achieved with a slight area penalty.

Abstract The great demand for mobile blockchain computing power is often unsatisfied by terminal devices, so computational tasks are offloaded to edge computing servers. This paper proposes a new mobile communication blockchain assumption, forms a computing power alliance (CPA), and builds a smart contract‐based security model. First, mining difficulty compensates for the personal computing power outside the CPA to increase the block generation difficulty. Second, contract account funds are used to increase the cost of malicious nodes seeking to launch forking attacks, and the duration is used to limit mining. Finally, a court trial is opened to select validators to verify the fork. The auction algorithm is used to allocate computing power in the CPA, and a price utility function is constructed to maximize social welfare. The joint optimization algorithm increases the transaction price and improves the system security. Simulation results verify that the system security increases with the blocked funds and duration, and the forking attack success rate approaches zero as the number of validators increases. The proposed algorithm provides considerable sum utility and average revenue gains versus traditional methods under different numbers of mobile users and computational capabilities, and the security of the algorithm is also higher.