The articles in this special issue focus on the history and development of light emitting diode (LED) technology and industry applications over the last fifty years.

A programmable delay locked loop (DLL) based clock generator, providing a high multiplication factor, has been developed in a 0.18- μm CMOS technology. Utilizing the proposed pulse generator, purely consisting of D flip flops (DFFs) and inverters, the clock generator provides a high multiplication factor of up to 24. It consumes only 16.2 mW when generating 2.16 GHz output signals. In addition, the proposed saturated-type unit delay cell adopted in the voltage controlled delay line (VCDL) is capable of providing a long delay while maintaining fast-switching signal edges. Thus, the DLL can lock up an input reference frequency as low as 30 MHz while maintaining good phase noise performance and small chip area occupancy. The phase noise is -88.7 and -99.8 dBc/Hz at 10 kHz and 100 kHz offsets, respectively, from the operating frequency of 1.2 GHz, which is equivalent to a 1.7 ps RMS jitter. The active chip area takes only 0.051 mm2.

The matrix determinant computation system (MDCS) is developed in subthreshold current-mode for an analog signal processing. By utilizing the translinear loop principle and the novel differential architecture, the MDCS can perform accurate addition, subtraction, and multiplication in analog domain. The system computes a 2-by-2 and 3-by-3 determinant with 91 % accuracy and a 3 kHz input can be handled while consuming 110.05μW. The overall system is fabricated on a 0.18μm CMOS technology and the area is 500μm × 800μm.

Linear amplification with nonlinear components (LINC) provide excellent linearity with high efficiency by adopting switch mode power amplifiers. One of the issues regarding LINC is the efficiency degradation due to wasted power at the power combiner when phase difference is large. In this paper, two efficiency enhancement architectures are presented: multi-level LINC (MLINC) architecture improves transmitter efficiency compared to a conventional LINC system, and the proposed uneven multi-level LINC (UMLINC) can further improve the efficiency. Another problem of LINC is the amplitude and phase mismatches between the two signal paths degrading the linearity performance. To address the problem, an unbalanced mismatch calibration technique for the proposed LINC system is introduced.

With the overwhelming adoption of Orthogonal Frequency Division Multiplexing (OFDM) technique in many recent wireless communications standards, there have been extensive approaches to tackle the high Peak-to-Average Power Ratio (PAPR) problem that yields low efficiency in RF power amplifiers, which is the major drawback of OFDM systems. One of the approaches is to replace power amplifiers with the Linear Amplification using Nonlinear Components (LINC) block. However, this produces additional nonlinear distortions caused by amplitude or phase mismatch between two power amplifiers inside the LINC block. In this paper, we introduce a noble LINC calibration technique that utilizes the channel estimator block that is initiated by the Media Access Control (MAC) layer during the Distributed Interframe Space (DIFS) or Short Interframe Space (SIFS). For DIFS or SIFS, pilot symbols are allocated in a payload field and then the outputs of the transmitter are internally forwarded to the receiver to characterize the LINC channel with a pilot-aided Least Square Error (LSE) channel estimator. By applying a reverse distortion onto information symbols after the LINC channel distortion is obtained by channel estimation, we can significantly improve the Symbol Error Rate (SER) and Error Vector Magnitude (EVM) of the OFDM system with the LINC transmitter.

The 19 papers in this special issue focus on the push beyond giga-bit-per-second (Gbps) data rates, in order to more rapidly access data on personal devices, as well as potentially replace all the cables going into a device, including the video cable. This issue beings together the state-of-the-art, across multiple disciplines, for achieving Gbps WPAN capability.

In this paper, we present four examples of highly integrated 60 GHz single-chip CMOS 90nm digital radios and phased array solutions. These solutions include for the first time digital-to-analog/analog-to-digital conversion and embedded multi-gigabit mixed signal modem requiring no external processing. This convergence of 60GHz CMOS digital radio, low power multi-gigabit mixed-signal processing and digital signal processing on a single chip offers the lowest energy per bit transmitted wirelessly at multi-gigabit rate to meet the very stringent low-power specifications for battery operated consumer electronic portable devices. Layout and temperature dependent 60GHz CMOS 90nm model development and critical high performance analog and mixed building blocks are presented as fundamental enablers for single chip integration. The designs have been optimized for robustness against process variation and temperature, and verified by measurement results.

A novel RF switch driver for high-power wireless applications is presented. The switch driver employs a novel structure of a charge pump to generate up-converted voltage to ensure linearity of an antenna switch made of GaAs p-HEMT technology. The novel charge pump can generate up-converted voltage that is higher than that of conventional charge pumps by using a parallel structure and PMOS body bias technique. The proposed switch driver was fabricated using a 0.35-um standard CMOS technology. The up-converted voltage reaches up to 8.6V with 3V-supply voltage and less than 30mV of ripple. The size of the chip is less than 0.12mm2.

A novel CMOS high power RF switch using the multi-gate structure in a 0.18-mum triple-well CMOS process is designed, implemented, and characterized. The receive switch incorporates the multi-gate structure in order to provide high power handling capability to the transmit switch side. In addition, the RF switch with the multi-gate structure reduces insertion loss more than the one with the stacked transistor by reducing parasitic capacitance to the substrate. For performance comparison purposes, a triple-gate, and dual-gate NMOS switch were fabricated and characterized. Experimental data show that the SPDT switch exhibits 26 dBm of P1dB with the triple gate structure, and 24 dBm of P1dB with the dual gate structure at 900 MHz and 1.9 GHz. The multi-gate switch demonstrates 0.2 dB lower insertion loss than the multi-stacked switch. The switch die is also minimized by employing the compact multi-gate layout structure. Compared to the multi-stacked structure using an RF NMOS device in standard CMOS process, the die size of the triple gate and the dual gate is reduced by 50 % in both cases.

In order for adaptive filter design to achieve optimum performance, the latency around the loop needs to be exactly designed for each targeted data rates. Due to unforeseen parasitic effects, latency has been major design issues for adaptive filters design with decision feedback topologies. In this paper, a digitally controlled adjustable delay line IC is presented that can be tuned with 3-ps resolution with a modular-based digital-to-analog converter (DAC) design. The proposed adjustable delay line achieved wide bandwidth for 10-Gb/sec data throughput while demonstrating bit-error rate (BER) improvement for the given equalizer design over various band-limited channels. The proposed IC is implemented in a 0.18-mum standard CMOS technology.

In this paper, a BiCMOS equalizer using an active delay line structure for backplane communication is investigated. Equalization is achieved using a finite impulse response (FIR) filter. The filter is implemented using variable gain blocks and delay elements. The variable gain function is implemented using a Gilbert cell topology, modified for high-speed application. The delay line is implemented using active devices. The active delay line consumes less area than a passive L-C delay line, and has improved bandwidth as well as performance over process variation. The equalizer is implemented in a 0.25-mum BiCMOS technology. To the best our knowledge, it is the first BiCMOS equalizer using an active delay line approach.

Digital interactive mobile broadcasting application realizes the delivery of multimedia service and new value-added services for consumers and business areas. Meanwhile, one of the challenging issues for its successful deployment is radio spectrum resource management for the interactive feature and the broadcasting of additional contents besides the existing digital TV programs. In this paper, a Cognitive Radio (CR)-based digital interactive mobile broadcasting application is introduced. User terminals may scan or sense the received spectrum to find the spectrum resource, which is effectively unused for the certain time, area and location. These additional spectrum resources may be recycled and utilized as the return channel spectrum resource for the interactive broadcasting feature. Moreover, this work suggested a wideband Multi-Resolution Spectrum-Sensing (MRSS) technique based on a wavelet transform and a tri-stage detection algorithm. Accordingly, the MRSS technique offers flexible spectrum-sensing resolutions providing accurate, reliable and fast detection performance. Simulations were performed for detection of the American digital TV

Although ultra wideband (UWB) is a promising wireless technology for the future due to its high data rate, low power consumption, and low cost, its worldwide acceptance is conditioned by coexistence issues because of the frequency overlap with other wireless standards such as WiMax. In many countries, a detect and avoid (DAA) scheme has been promoted as a means to mitigate interference and it is now regarded as an indispensable solution for commercialization of UWB. A detailed specification for DAA can be determined by analyzing co-channel interference for a victim receiver. This paper presents a quantitative interference analysis using desired to undesired (D/U) signal power ratio as well as verification results using an equipment-based WiMax testbed. Finally, the D/U ratio results were used to determine minimum keep-out distance and the sensing threshold level for DAA in a UWB device.

Spectrum sensing technology is most vital to the implementation of a CR system using dynamic spectrum resource management. This paper suggested a CR system architecture with a wideband dual-stage spectrum sensing technique - a coarse and a fine spectrum sensing. Specifically, a coarse spectrum sensing technique adopted wavelet transforms in this architecture to provide a multi-resolution spectrum sensing (MRSS) feature. Analog implementation of the MRSS block offers wideband, low-power, and real-time operation. A fine spectrum sensing technique used the beneficial properties of auto-correlation in time domain - temporal signature detection (TSD). This TSD technique enables identifying the unique signature feature of each specific signal type. Moreover, this feature detection technique in time domain realizes simple and fast spectrum-detection compared to spectral feature detection methods.

In order to realize adjustable equalization over various backplane channel configurations, a reconfigurable fully-integrated equalizer IC is presented. Backplane channels over different trace lengths and dielectric materials were measured and characterized. Feed-forward equalizer (FFE) topology with finite impulse response (FIR) architecture was chosen for optimal equalization for the corresponding backplane configurations. For a reconfigurable FFE IC implementation, wide-range tunable active delay line, variable tap-gain multiplier and 8-bit digital-to-analog converter (DAC) were fabricated in a 0.18-mum standard CMOS technology. The proposed reconfigurable FFE demonstrated successful equalization at 10Gb/sec over various channel configurations

Spectrum sensing technology is most vital to the implementation of a CR system using dynamic spectrum resource management. This paper suggested a CR system architecture with a wideband dual-stage spectrum sensing technique - a coarse and a fine spectrum sensing. Specifically, the coarse spectrum sensing technique adopted wavelet transforms in this architecture to provide a multi-resolution spectrum sensing (MRSS) feature. Analog implementation of the MRSS block offers wideband, low-power, and real-time operation. From the system simulation results, MRSS achieved 15-, 20-, and 30-dB detection margin for FM, VSB, and OFDM signals, having the corresponding signal power of -110, -120, and -120 dBm, respectively

This paper investigates the performance of passive and active inductors for digital Si-CMOS technologies. The extreme low-resistivity of the Si-substrate and the absence of thick top metal layers in digital-CMOS processes prevent the implementation of high-Q passive inductors, and demand alternate solutions. A detailed comparison between the active and passive inductors based on several performance criteria such as Q-factor, area, tunability, noise, linearity, EMI, floor-planning etc reveals the tremendous potential of the high-Q tunable active inductors. An optimization guideline for the grounded-inductor topology has also been suggested. As a basis of comparison, oscillators have been implemented using both the inductors. The active inductor VCO achieves a much higher tuning range and occupies a much smaller die-area than the passive implementation at the cost of degraded phase-noise performance

In this paper, the performance degradation of a MIMO OFDM-based beyond-3G system, due to various impairments in the radio frequency (RF) circuitry such as AM-AM distortion of power amplifier (PA), in-phase/quadrature-phase (IQ) mismatch effects, is investigated. In order to accurately assess the overall effects of RF impairments on the system performance, constellation diagram and power spectral density (PSD) of the waveform as well as the traditional quantitative figures of merits like error vector magnitude (EVM) of the complete baseband/RF link are used. By analyzing the experimental results, the specification for the RF impairments that ensures a tolerable level of performance can be determined

A cognitive radio (CR) access technique is a promising solution for the dynamic spectrum resource usage. This paper presented a CR testbed system employing a wideband multi-resolution spectrum sensing (MRSS) technique. Analog implementation of the MRSS block offers wideband, low-power, and real-time operation. The MRSS experiments were performed using the developed CR testbed system. The experiment results showed that the MRSS technique detected wideband 100-MHz spectrum in a sparse or a precise manner without any increase of hardware burden. Moreover, this MRSS technique detected a variety of sophisticated signal formats adopted in the current and emerging wireless standards - IS-95, WCDMA, GSM, EDGE, Wi-Fi (IEEE802.Ha/b/g), ATSC, DVB, etc.

The system-on-a-package (SOP) concept is considered as the solution of future communication modules, where more functionality, better performance, low cost, and more integrity is needed. We demonstrate how SOP technology can address the integration platform for future communication systems, especially gigabit wireless communications. After the introduction of the SOP concept, we introduce the critical design building blocks which are required in a viable SOP technology: integrated passives, embedded RF functions, including high-performance filters and baluns, and integrated antenna technologies. Second, we review how the three-dimensional deployment of core elements, such as baluns, lumped inductors, capacitors, and resistors, as well as IF or low-pass filters, enables RF-SOP module development. We demonstrate how advanced radio architectures, including direct conversion, antenna diversity, and collaborative signal processing, are enabled using the SOP technology format. Various ceramic and organic material based multilayer packaging technologies have been used for building such integrated modules as well as circuit blocks. The critical issues and challenges for developing advanced communication platforms using the SOP approach are discussed.