We present designs for in-circuit monitoring of custom hardware designs implemented in reconfigurable hardware. The monitors check hardware designs against temporal logic specifications. Compared to previous work, which uses custom hardware to monitor software, our designs can run at higher speeds and make better use of hardware resources, such as shift registers and embedded memory blocks. We evaluate our monitor circuits on example hardware designs targeting FPGA implementation, showing that they have low overhead in terms of circuit area, and can run at the same speed as the circuits they monitor.

Massively parallel processing architectures mimicking biological structures and their underlying calculation principles have been put into practice by the members of the cellular neural network (CNN) community. But until now flexible, scalable and industrially qualified toolkits are not available to support the simulation and development of these architectures within one single environment. In this paper we report on a simulation-framework, which is conceptualized and adjusted to deal with the specific simulation requirements of purely digital CNN processing devices. In particular, the framework is able to (1) handle complete CNN architectures of industrial relevant size, (2) to represent double precision float-point numbers as well as hardware relevant fixed-point numbers and (3) offer simulation run-times a magnitude faster than standard digital hardware simulations. We conclude this paper by presenting selected simulation results manifesting the proposed capabilities of the simulation-framework.