Rapid adoption of smartphones and tablets in recent years has changed the way people communicate with each other and operate in the work environment. The use of personal devices in the enterprise has become commonplace. These devices have given workers the flexibility of being mobile and still participate in collaboration sessions. However, transferring sessions between devices is not very seamless and causes disruptions in the sessions, resulting in an unsatisfactory user experience. This work presents an architecture and implementation for seamless session mobility across different types of devices and hardware/software platforms. This architecture is not restricted to a specific collaboration server and can accommodate multi-vendor environments.

There are two broad categories of approaches used for checkpointing: application-transparent and application-assisted. Typically, application-assisted approaches provide a more flexible and light-weight mechanism but require changes to the application. Although most applications run well under virtualization (e.g. Xen which is being adopted widely), the addition of application-assisted checkpointing - used for high availability - causes performance problems. This is due to the overhead of key system calls used by the checkpointing techniques under virtualization. To overcome this, we introduce the notion of hypervisor-assisted application checkpointing with no changes to the guest operating system. We present the design and a Xen-based implementation of our family of application checkpointing techniques. Our experiments show performance improvements of 4× to 13× in the primitives used for supporting high availability compared to purely user-level approaches.

Virtualization provides enormous economic and ecological benefits by enabling server consolidation and supporting low-cost green data centers. A key component of the hypervisor in a virtualized system is the scheduler. A typical scheduler provides parameters to influence the hypervisor's behavior. Specifically, an application's performance on the popular open-source Xen virtualization platform can be influenced by tuning its scheduler behavior using the weight, cap, and processor pinning variables. However, determining which parameters to tune and how to do that is non-trivial. In this paper, we introduce XenTune, a monitoring tool for the credit scheduler in Xen that helps in understanding application behavior in scheduler terms and assists in determining scheduler parameters. We demonstrate how the tool is used with application domains - specifically a media application domain. We demonstrate experimental results using a real work-load that shows the considerable benefits of correct scheduler parameter choices. XenTune had helped in the design of a recently proposed scheduler S and in this paper we show how scheduler S interacts with the media application to optimize its performance.

Virtualization technology enables server consolidation and has given an impetus to low-cost green data centers. However, current hypervisors do not provide adequate support for real-time applications, and this has limited the adoption of virtualization in some domains. Soft real-time applications, such as media-based ones, are impeded by components of virtualization including low-performance virtualization I/O, increased scheduling latency, and shared-cache contention. The virtual machine scheduler is central to all these issues. The goal in this paper is to adapt the virtual machine scheduler to be more soft-real-time friendly.

Multi-hop ad-hoc wireless networks need additional software at each node to provide routing functionality. There is significant benefit in supporting legacy devices (i.e., devices that do not have any additional routing software) in such networks. In this paper, we present a system and techniques for legacy device support in multi-hop ad-hoc wireless networks. One conceptual approach is to enable access point-like support at each multi-hop ad-hoc node that allows the legacy devices to associate in infrastructure mode. In contrast, we present a novel scalable architecture that extends the benefits of path redundancy inherent in multi-hop ad-hoc networks to legacy devices and also supports mobility. Using the legacy device as a message reflector in a transparent manner allows the system to make decisions in a light-weight distributed fashion. We describe our architecture, protocols and a prototype system. We also present some analysis and observations from the prototype.

In this paper, the authors motivate the interesting characteristics of small-to-medium enterprises and study the problem of wireless IP telephony for such deployments. While small enterprises are characterized by few network nodes and small deployment areas, they also demand good IP telephony quality, ease of deployment, and low management and configuration overhead. The authors evaluate the feasibility of peer-to-peer telephony over a multi-hop wireless ad-hoc network for such small enterprises. The authors designed a system and built a prototype using off-the-shelf components. In this paper, the authors describe the implementation and deployment of this system. Several fundamental routing protocol issues needed to be resolved to develop a stable system and the authors present them here. The authors also report the results of a simulation study they conducted to establish the configuration and performance parameters for such systems, and identify the limits to the use of multi-hop ad-hoc wireless for peer-to-peer IP telephony for small enterprises.

Location estimation enables many innovative applications and is an exciting area of research. With the growing use of wireless technology in enterprise networks, it is an interesting technical challenge to develop techniques for indoor location estimation that leverage the deployed wireless infrastructure. Elegant, cost-effective techniques would present a compelling business proposition. In this paper, we summarize various approaches researchers have studied for the problem of indoor location estimation, concentrating on signal-strength based techniques directed towards 802.11 wireless networks. We also summarize an interesting insight into the best possible accuracy achievable by any technique due to limits imposed by the physical behavior of the radio signal. We identify that the issues driving research work in this area will not only be location accuracy, but other factors like deployment ease, management simplicity, adaptability, and cost of ownership and maintenance. We conclude with some open research problems in this area

In this paper, we address the problem of finding the inherent uncertainty of signal strength-based location estimation techniques. We propose a mathematical model for mapping uncertainty in signal strength space to uncertainty in physical space. We then analyze this model to compute the minimum value of the uncertainty in location estimation using signal strength measurements. The results of this analysis are used to draw conclusions about the dependence of the minimum uncertainty of various factors such as the signal variance, number of APs, distance between the APs and the propagation constant. We provide an argument linking the minimum uncertainty with a lower limit on the median error in location estimation using classification techniques.

In this paper, we introduce a new approach to location estimation where, instead of locating a single client, we simultaneously locate a set of wireless clients. We present a Bayesian hierarchical model for indoor location estimation in wireless networks. We demonstrate that our model achieves accuracy that is similar to other published models and algorithms. By harnessing prior knowledge, our model eliminates the requirement for training data as compared with existing approaches, thereby introducing the notion of a fully adaptive zero profiling approach to location estimation.

With the advent of the IEEE 802.11e QoS standard, an interesting issue that arises is the provision of QoS support for legacy 802.11 terminals. In this paper, we present an access point-based overlay to the 802.11 DCF protocol that provides priority access to standard endpoints without requiring any client modifications. This technique can be used to provide preferential channel access to legacy endpoints in 802.11 networks, thus allowing the use of legacy 802.11 equipment even with such legal requirements. The use of clear-to-send (CTS) frames underlies this technique and hence we call it CATS, the CTS-assisted transmission scheme. Our technique works by positioning a quiet window straddling the expected time when a protected endpoint becomes ready to transmit. We present two variants of our method depending on whether or not the access point (AP) is able to directly observe the signaling. Using time-stamped traces of VoIP frames, we evaluate the performance of CATS. We also provide a simplified efficiency analysis of CATS.

Estimating the signal strength coverage of a wireless access point (AP), given its desired location at a site, is essential in many instances, e.g., to determine optimal AP placement. In this paper, we present a new non-parametric modeling solution, based on sampling, for this problem. We use sample measurements from several fixed APs in a novel way to compute a signal coverage model for an AP at a random location. Our technique automatically takes into account the signal strength propagation characteristics of the site and also allows for an efficient deployment methodology. We present an experimental study that validates the practical usability of the proposed technique.

Current "best practice" recommendations for enterprise wireless deployments suggest the use of VPNs from a wireless client for both authentication and privacy. In this paper, we demonstrate a security issue with such deployments, which we refer to as the hidden wireless router vulnerability. This vulnerability is inherent in the VPN-based wireless LAN architecture, and leads to unsuspecting clients becoming conduits for an attack, exploiting features readily available in popular operating systems like Windows and Linux. We describe the attack scenario, and possible solutions for both detecting and locating such hidden wireless routers. Our solutions include a range of possibilities stretching from purely passive to active probing methods, and access point-based solutions. We describe our techniques and results of our implementation and experiments.

We present LEASE, a new system and framework for location estimation assisted by stationary emitters for indoor RF wireless networks. Unlike previous studies, we emphasize the deployment aspect of location estimation engines. Motivated thus, we present an adaptable infrastructure-based system that uses a small number of stationary emitters (SEs) and sniffers employed in a novel way to locate standard wireless clients in an enterprise. We present the components of the system and its architecture, and new non-parametric techniques for location estimation that work with a small number of SEs. Our techniques for location estimation can also be used in a client-based deployment. We present experimental results of using our techniques at two sites demonstrating the ability to perform location estimation with good accuracy in our new adaptable framework.

This paper focuses on fundamental system deployment aspects of location estimation in 802.11-based wireless networks. We concentrate on adaptable infrastructure-based approaches, where sniffers measure received signal strength from clients to locate them. Our implementation experience and experimental results show that sniffer-based location estimation is feasible and works well provided some important rules are followed. By studying data over a 6-month period, we observe that adaptation of models is necessary for good location estimation, and we show that our techniques enable location estimation with minimal profiling. We also present an intriguing client-assisted approach for location estimation where a client, APs and sniffers collaborate to locale a terminal in enterprise (infrastructure-mode) wireless networks.

Carrier sense multiple access (CSMA) is one of the most pervasive medium access control (MAC) schemes in ad hoc, wireless networks. However, CSMA and its current variants do not provide quality-of-service (QoS) guarantees for real-time traffic support. This paper presents and studies black-burst (BB) contention, which is a distributed MAC scheme that provides QoS real-time access to ad hoc CSMA wireless networks. With this scheme, real-time nodes contend for access to the channel with pulses of energy-so called BBs-the durations of which are a function of the delay incurred by the nodes until the channel became idle. It is shown that real-time packets are not subject to collisions and that they have access priority over data packets. When operated in an ad hoc wireless LAN, BB contention further guarantees bounded and typically very small real-time delays. The performance of the network can approach that attained under ideal time division multiplexing (TDM) via a distributed algorithm that groups real-time packet transmissions into chains. A general analysis of BB contention is given, contemplating several modes of operation. The analysis provides conditions for the scheme to be stable. Its results are complemented with simulations that evaluate the performance of an ad hoc wireless LAN with a mixed population of data and real-time nodes.

EQuB is an overlay mechanism to Ethernet's MAC protocol that provides QoS guarantees to real-time applications. In its basic form, EQuB relies on the sensing and collision detection abilities of standard network interface cards and, in addition, requires only that those cards be capable of sending jam signals-so called black bursts-of pre-specified durations. EQuB gives access priority to real-time traffic, provides round-robin service among real-time hosts and guarantees a small, bounded delay to real-time packets. We also discuss enhancements to the basic EQuB mechanism that improve its performance. Simulation results are presented that assess the performance of 10 and 100 BASE-T Ethernet LANs with a mixed population of data and real-time hosts. We conclude that, in spite of the priority, attained by real-time traffic, data packer delays are not significantly affected as data load is traded for real-time load, and this is because EQuB dispatches packets to the channel much more efficiently than Ethernet's MAC protocol.

We present a method of automatic generation of functional vectors for sequential circuits. These vectors can be used for design verification, manufacturing testing, or power estimation. A high-level description of the circuit in VHDL or C is assumed available. Our method automatically transforms the high-level description of a circuit in VHDL or C into an extended finite state machine (EFSM) model that is used to generate functional vectors. The EFSM model is a generalization of the traditional state machine model. It is a compact representation of models with local data variables and preserves many nice properties of a traditional state machine model. The theoretical background of the EFSM model is addressed in this article. Our method guarantees that the generated vectors cover every statement in the high-level description at least once. Experimental results show that a set of comprehensive functional vectors for sequential circuits with more than a hundred flip-flops can be generated automatically in a few minutes of CPU time using our prototype system.

In this paper, we present a method to compute symbolically, the set of con gurations reachable from the initial con guration of an Extended Finite State Machine.Our representation allows variables of arbitrary type (boolean, arithmetic etc.) to be freely mixed.We de ne a class of EFSMs called direct sum machines and show h o w the reachable set of con gurations for this class can be computed.In the computation, we use a hybrid model to represent sets of con gurations.Sets of states formed by boolean variables are represented by BDDs and sets of states formed by arithmetic variables are represented as polyhedral regions.This method can be adapted to perform validation, veri cation, test generation etc. for sequential machines.We describe an implementation of this approach and the results of applying it to some design examples. 31

The protocol VLSI engine (PROVE) is programmable VLSI chipset which can be used to implement several standard communication protocols. The protocol to be implemented is described in a formal specification language called the augmented protocol specification language (APSL). From these formal descriptions, a compiler generates microcode for PROVE. PROVE can process 50000 packets/s for standard protocols such as LAPD and LLC Class 2. It consists of a message parser (MP), message assembler (MA), central controller unit (CCU), and interface with the upper layer. It supports efficient multiplexing operation with zero-overhead context-switching and support for timer maintenance. The paper describes the architectural features of the CCU, the MP, and the MA. A typical protocol implementation using the PROVE chipset is also described. The authors also compare it with other proposals for protocol engines. The first generation of the PROVE chipset has been built and tested.>

We present a method of automatic generation of functional vectors for sequential circuits. A high-level description of the circuit, in VHDL or C, is assumed available. Our method automatically transforms the high-level description, in VHDL or C, of a circuit into an extended finite state machine (EFSM) model using which functional vectors are generated. The EFSM model is a generalization of the traditional state machine model. It can be considered as a compact representation of the machine that preserves many nice properties of a traditional state machine. Theoretical background of the EFSM model will be addressed. Our method guarantees that the generated vectors cover every statement in the high-level description at least once. Experimental results show that a set of comprehensive functional vectors for sequential circuits with more than a hundred flip-flops can be generated automatically in a few minutes of CPU time using our prototype system.

Design verification is the process of checking that the specification of a circuit satisfies certain correctness properties. Approaches to design verification have involved the use of temporal logic and model checking, as well as the use of higher-order logic and theorem proving. Current approaches suffer from either limited expressivity of the logic, the state explosion problem, or difficulty in automating the verification process. The primary source of the complexity explosion in automata theoretic or temporal logic approaches is the state space explosion due to the need to construct the state space of the system under analysis. Symbolic analysis techniques are used based on linear algebra, specifically matrix multiplication, to compactly represent the state space of circuits described by a behavioral or register-transfer-level specification and thereby avoid this state space explosion, for classes of circuits.>

Several protocol controllers for the IEEE 802 local area networks are surveyed and some characteristics for classifying them are given. Some case studies from these controllers are given as illustrations. Two new developments-the protocol engine and the programmable protocol engine-are also described. The protocol engine, currently under development, implements a new protocol called XTP which performs the functions of both the network and transport layers. The programmable protocol engine can implement several connection-oriented protocols by changing contents of a programmable random access memory.>

MARS (Microprogrammable Accelerator for Rapid Simulations) is a multiprocessor based hardware accelerator capable of efficiently implementing a wide range of computationally complex algorithms. Its architecture is ideally suited for performing event driven simulations of VLSI circuits. The highly pipelined and parallel architecture of MARS provides a performance comparable to existing hardware simulation engines while its highly flexible architecture supports a wide range of applications. Flexibility is achieved through custom designed microprogrammable and reconfigurable VLSI processors. Logic simulation performance of about one million events per second is easily achievable.

In this paper, we present a divide-and-conquer approach to the evaluation of the characteristic polynomial of a symmetric tridiagonal matrix for a real argument. Here, the problem is partitioned into smaller parts which are solved and these solutions are then combined to form the solution to the original problem. We give the update equations for the characteristic polynomial and certain auxiliary polynomials used in the computation. We show that the three-term recurrence is a specific case of our equations. Furthermore, this set of recursions can be implemented on a regular tree structure. If the concurrency exhibited by order is increased by one at every step.