Computing systems working in harsh environment is prone to suffer from radiation-induced soft errors; for example, Single Event Upsets (SEUs) and Single Event Transients (SETs) are the major reliability issue for circuits fabricated with nanoscale technology nodes. In this paper, we proposed a low-cost SET and SEU error tolerant flip-flop (SETU-TOFF). Based on the traditional flip-flop, two high-level sensitive redundant latches are added to latch the input data at different times, and a voter is designed for the correct output. It removes the timing overhead of temporal redundancy from the critical path of the systems. Comparing with the existing designs presented in literatures, SETU-TOFF has comprehensive fault tolerant capability with lower overheads; moreover, it doesn’t increase significant latency of the flip-flops. We use the SETU-TOFF cells to protect a pipeline of an OpenRISC microprocessor. Fault injection simulations show that SETU-TOFF can achieve 100% protection for the pipeline with negligible performance loss; additionally, it can detect and correct errors in real time without extra system control logic and clocks for errors recovery.

As technology scaling down, the sensitivity of SRAM cells to radiation-induced Single Event Upsets (SEUs) increases, and Single Event Multiple Node Upsets (SEMNUs) due to charge sharing has also become one of the major concerns in memory cell designs. In this paper, a high-reliability radiation hardened memory cell (RH-14T) is proposed to mitigate SEMNUs. SPICE simulations and 3D technology computer aided design mixed-mode simulations were performed to verify the high robustness of the RH-14T cell to SEUs. Compared with previous radiation hardened memory cells, the proposed RH-14T cell has similar read access time, smaller write access time, and the read access time and write access time are less sensitive to process variations. The Read Static Noise Margin (RSNM) and Write Margin (WM) of the RH-14T cell are larger than those of the unhardened conventional 6T SRAM cell. The improvement of reliability is often a trade-off with area, power consumption and performance. In order to achieve high reliability, the RH-14T cell employs more transistors, so it has 1.5 times the power consumption overhead of 6T and a larger area penalty.

Field programmable gate array (FPGA) is becoming more valuable for space applications because of its large density, high performance, reduced development cost and flexible programmability. In particular, static random access memory (SRAM) based FPGA is very valuable for remote missions because of the possibility of being reprogrammed by the user as many times as necessary in a very short period. However, SRAM-based FPGA contains a large number of memory cells which are very sensitive to single event upset (SEU). SEU in SRAM-based FPGA may result in a functional error unless the FPGA is reconfigured. In this paper, we propose a fast adjustable scrubbing method based on Xilinx essential bits technology to mitigate the effect of SEU for SRAM-based FPGA. The whole scrubbing flow contains two sub-flows: partial scrubbing and entire scrubbing. This scrubbing method not only increases the speed of repairing an error for user design, but also ensures the reliability of whole FPGA design. We test the proposed scrubbing method through fault injection. Finally, we show the error repair speeds of user designs for different repeat cycles of partial scrubbing and summarize the optimized repeat cycles of partial scrubbing.

Radiation-induced single event transients (SETs) are expected to evolve to single event multiple transients (SEMTs) due to the downscaling of transistor feature size, which also increases the difficulty of the vulnerability estimation for large-scale digital integrated circuits. In this paper, a novel layout-based soft error vulnerability estimation approach which is termed LBSEVEA is proposed to evaluate the impact of heavy ions on the vulnerability of combinational circuits. The physical process of interaction between particles and devices, especially nuclear reaction and scattering process are included in the LBSEVEA. In addition, ambipolar diffusion and bipolar amplification effect, which induce additional charge collection of the adjacent transistors and the hitting transistor, are also considered. A new method calculating the collected charge induced by the bipolar amplification effect is presented. By introducing the layout information of the target circuits into the identification of the adjacent cells, SEMTs effect can be considered in the vulnerability estimation. A fast SPICE simulation tool is adopted to conduct the fault injected netlist simulations, which can make a favorable compromise between the consumption of computer resources and simulation precision. Furthermore, induced soft error numbers, distributions of charge collected by the hitting nodes and the adjacent nodes, and SET pulse width distributions are presented. Besides, heatmaps of induced pulse widths for the layout of two benchmark circuits are provided. Finally, the constraints, the flexibility, and the scalability of the LBSEVEA are discussed. The ability to estimate the impact of process variations on the vulnerability is also presented. Compared with simulation and experimental results, the LBSEVEA can fairly estimate the vulnerability of combinational circuits.

Soft errors caused by particle strike in combinational circuits are a major concern in the design of reliable circuits. Particle strike induced single event transient (SET), especially the evolutional single event multiple transients (SEMTs) in nanoscale CMOS technologies, has been the non-negligible reliability issue for hardening design of combinational circuits. This paper presents a low overhead method to protect combinational circuits against particle strike. This method is made up of a combination of two sub-method: (1) a soft error sensitivity estimation method, called Layout-Based Multiple Event Probability Propagation (LBMEPP) and (2) a protection method based on gate sizing, called Intelligent optimization-Based Gate Sizing (IOBGS). Unlike the previous techniques that either overlook the SEMTs event or exploit fault injection. LBMEPP can provide the sensitivity estimation of combinational circuits in the presence of SET and SEMTs. The SEMTs adjacent cells are identified by the cell's layout and Geant4 Monte Carlo simulation. Therefore, the SEMTs event can be considered in the sensitivity estimation. Using the estimation result of LBMEPP, IOBGS adopts multi-objective particle swarm optimization algorithm to dynamically allocate and adjust each logical cells. In IOBGS, SER, circuit area and longest path delay of the circuit are selected as the optimization goals. The experiments conducted on several typical circuits show that the proposed optimization method can evidently decrease the SER with a limited overhead.

The use of error-correction codes (ECCs) with advanced correction capability is a common system-level strategy to harden the memory against multiple bit upsets (MBUs). Therefore, the construction of ECCs with advanced error correction and low redundancy has become an important problem, especially for adjacent ECCs. Existing codes for mitigating MBUs mainly focus on the correction of up to 3-bit burst errors. As the technology scales and cell interval distance decrease, the number of affected bits can easily extend to more than 3 bit. The previous methods are therefore not enough to satisfy the reliability requirement of the applications in harsh environments. In this paper, a technique to extend 3-bit burst error-correction (BEC) codes with quadruple adjacent error correction (QAEC) is presented. First, the design rules are specified and then a searching algorithm is developed to find the codes that comply with those rules. The ${H}$ matrices of the 3-bit BEC with QAEC obtained are presented. They do not require additional parity check bits compared with a 3-bit BEC code. By applying the new algorithm to previous 3-bit BEC codes, the performance of 3-bit BEC is also remarkably improved. The encoding and decoding procedure of the proposed codes is illustrated with an example. Then, the encoders and decoders are implemented using a 65-nm library and the results show that our codes have moderate total area and delay overhead to achieve the correction ability extension.