In the last few years, Federated Learning (FL) has received extensive attention from the research community because of its capability for privacy-preserving, collaborative learning from heterogeneous data sources. Most FL studies focus on either average performance improvement or the robustness to attacks, while some attempt to solve both jointly. However, the performance disparities across clients in the presence of attackers have largely been unexplored. In this work, we propose a novel Fair Federated Learning scheme with Attacker Detection capability (abbreviated as FFL+AD) to minimize performance discrepancies across benign participants. FFL+AD enables the server to identify attackers and learn their malign intent (e.g., targeted label) by investigating suspected models via top performers. This two-step detection method helps reduce false positives. Later, we introduce fairness by regularizing the benign clients’ local objectives with a variable boosting parameter that gives more emphasis on low performers in optimization. Under standard assumptions, FFL+AD exhibits a convergence rate similar to FedAvg. Experimental results show that our scheme builds a more fair and more robust model, under label-flipping and backdoor attackers, compared to prior schemes. FFL+AD achieves competitive accuracy even when 40% of the clients are attackers.

We considered an approach to identify vehicle through recognizing of it license plate using image fusion, neural networks and threshold techniques as well as some experimental results to recognize the license plate successfully.

The question of how to learn rules, when those rules make probabilistic statements about the future, is considered. Issues are discussed that arise when attempting to determine what a good prediction function is, when those prediction functions make probabilistic assumptions. Learning has at least two purposes: to enable the learner to make predictions in the future and to satisfy intellectual curiosity as to the underlying cause of a process. Two results related to these distinct goals are given. In both cases, the inputs are a countable collection of functions which make probabilistic statements about a sequence of events. One of the results shows how to find one of the functions, which generated the sequence, the other result allows to do as well in terms of predicting events as the best of the collection. In both cases the results are obtained by evaluating a function based on a tradeoff between its simplicity and the accuracy of its predictions.>

In [2] Savir, Ditlow, and Bardell presented an algorithm for estimating the signal probability of a line in combinational circuits, but were unable to show that the algorithm always produced correct results. This paper shows that their algorithm for cutting reconvergent fan-out lines in a circuit eventually produces a circuit without reconvergent fan- out that can be used to estimate signal probabilities in all lines of the original circuit.

With the advent of VLSI, testing has become one of the most costly, complicated, and time consuming problems. The method of syndrome- testing is applicable toward VLSI testing since it does not require test generation and fault simulation. It can also be considered as a vehicle for self-testing. In order to employ syndrome-testing in VLSI, we electronically partition the chip into macros in test mode. The macros are then syndrome tested in sequence.

In [1] and [2] Savir developed many facets of syndrome-testing (checking the number of minterms realized by a circuit against the number realized by a fault-free version of that circuit) and presented evidence showing that syndrome-testing can be used in many practical circuits to detect all single faults. In some cases, where syndrome-testing did not detect all single stuck-at-faults, Savir showed that by the addition of a small number of additional "control" inputs and gates one would get a function which is syndrome-testable for all single stuck-at faults, and yet which realizes the original function when the "control" inputs are fed appropriate values. However, he left open the question of whether one could always modify a circuit to achieve syndrome-testability. In this correspondence we show that a combinatorial circuit can always be modified to produce a single-fault, syndrome-testable circuit.

This paper analyzes a method for identifying end-to-end connections in computer networks which is designed to provide reductions in the sizes of the packet headers and routing tables stored in the nodes. The method, known as Local Path ID Swapping, uses a shortened connection identifier, called the LPID, in the message headers and routing tables. In general, the LPID field is swapped in the message header from node to node along the path of the route. Some analytical results are presented for evaluating the important tradeoffs involved in LPID swapping. Most notable is the tradeoff between the size of the LPID field and the number of connections which can be defined in the network.

Three famdies of strategies for orgamzmg an index of ordered keys are investigated It ~s assumed either that the index is small enough to fit m mam memory or that some superstrategy orgamzes the index into pages and that search within a page is being studied Examples of strategies within the three families are B-tree Search, Binary Search, and Square Root Search The expected access times of these and other strategies are compared, and their relative merits in different indexing situations are d,scussed and conjectured on Considering time and space costs and complexity of programming, it Is concluded that a Binary Search strategy is generally preferable

We show how to construct, in a simple manner, a test set having n + 1 tests for a fanout-free combinational circuit with n primary inputs which distinguishes (diagnoses) nonequivalent single faults. This result is an improvement over the upper bound in [1, Theorem 3.9] of n + g (g is the number of primary input gates) and the upper bound in [3, Theorem 4], [5] of 2n for the least number of tests required to distinguish among nonequivalent single faults.

In this paper we consider the question of how much space is needed to represent a set. Given a finite universe U and some subset V (called the vocabulary), an exact membership tester is a procedure that for each element s in U determines if s is in V. An approximate membership tester is allowed to make mistakes: we require that the membership tester correctly accepts every element of V, but we allow it to also accept a small fraction of the elements of U - V.

Given partially ordered sets (posets) P and Q, it is often useful to construct maps g:P→Q which are chain-continuous: least upper bounds (supremums) of nonempty linearly ordered subsets are preserved. Chaincontinuity is analogous to topological continuity and is generally much more difficult to verify than isotonicity: the preservation of the order relation. This paper introduces the concept of an extension basis: a subset B of P such that any isotone f:B→Q has a unique chain-continuous extension g:P→Q. Two characterizations of the chain-complete posets which have extension bases are obtained. These results are then applied to the problem of constructing an extension basis for the poset [P→Q] of chain-continuous maps from P to Q, given extension bases for P and Q. This is not always possible, but it becomes possible when a mild (and independently motivated) restriction is imposed on either P or Q. A lattice structure is not needed. Finally, we consider extension bases which can be recursively listed and derive a recently established theorem as a corollary.