This article consists of a collection of slides from the author's conference presentation.

The fabless ASIC model has changed the landscape of ASIC design by offering a high-quality, cost-effective and open alternative to realizing ASICs. The very nature of this model (because of its reliance on the third-party foundry, IP ecosystem) offers unique challenges and opportunities for implementing low power chips. This tutorial presents an overview of the exciting low power challenges, opportunities and solutions available in a fabless ASIC model. We review state-of-the-art low power IC solutions and case studies from varied markets, including processor-based, wired, wireless, consumer and multi-core chips.

With the advent of deep-submicron technologies, it has become essential to model the impact of physical/layout effects up front in all design flows \citeITRS02. The effect of layout parasitics is considerable even at the intra-cell level in standard cells. Hence, it has become critically important for any transistor-level optimization to consider the effect of these layout parasitics as an integral part of the optimization process. However, since it is not computationally feasible for the actual layout to be a part of any such optimization procedures, we propose a technique that estimates cell layout characteristics without actually performing the layout and subsequent extraction steps. We demonstrate in this work that it is indeed feasible to estimate the layout effects to get timing characteristics that are on average within about 1.5\% of post-layout timing and that the technique is thousands of times faster than the actual creation of layout.

Efficient identification of fault equivalence relations is essential for effective diagnostic test pattern generation. In this paper, we present efficient techniques for identifying functionally equivalent faults in combinational circuits. The techniques are based on implication of faulty values, and evaluation of faulty functions in cones of dominator gates of fault pairs. This is enhanced by utilizing circuit redundancy information. Both static and dynamic methods are developed to exploit relations among inputs of dominator cones and further speed up the identification of equivalent fault pairs. Experimental results for all ISCAS'85 circuits, full scan versions of ISCAS'89 circuits, and ITC'99 circuits show that most of the equivalent fault pairs are identified. Significant reductions are obtained in the runtime needed to prove equivalence and the runtime for diagnostic test pattern generation compared to previously proposed approaches.

This paper presents an efficient BIST solution for VLSI circuit testing based on GF(2p) CA (Cellular automata on an extended Galois Field). The novel architecture of GF(2p)) CA permits the BIST structure to be highly customized to the circuit under test (CUT). A methodology has been proposed to optimize the design of GF(2p) CA structure to maximize the fault coverage in a given CUT. In addition, an innovative scheme based on logic folding is presented to reduce the BIST overhead and make it more effective for large circuits.

A procedure for identifying functionally equivalent faults and improving the performance of diagnostic test pattern generation is described in this paper. The procedure is based on evaluation of faulty functions in cones of dominator gates of fault pairs. This is enhanced by utilizing circuit redundancy information. Equivalence is proved without the previously required circuit transformations. Stem-branch equivalences for reconvergent stems and their branches are identified efficiently obviating the need to check for non-masking and multiple-path sensitization. Both static and dynamic techniques are developed to exploit relations among inputs of dominator cones. This reduces the simulation time required by the procedure and enables evaluation of larger cones than could be evaluated earlier. As a result, more equivalent fault pairs are identified. Experiments performed on ISCAS85 circuits and full scan ISCAS89 circuits are used to demonstrate the effectiveness of the proposed techniques.

In this paper, we address an important problem associated with hierarchical design flows (termed the mapping problem): identifying correspondences between a signal in a high-level specification and a net in its lower level implementation. Conventional techniques use shared names to associate a signal with a net whenever possible. However, given that a synthesis flow may not preserve names, such a solution is not universally applicable. This work provides a robust framework for establishing register-transfer level (RTL) signal to gate-level net correspondences for a given design. Our technique exploits the observation that circuit diagnosis provides a convenient means for locating faults in a gate-level network. Since our problem requires locating gate-level nets corresponding to RTL signals, we formulate the mapping problem as a query whose solution is provided by a circuit diagnosis engine. Our experimental work with industrial designs for many mapping cases shows that our solution to the mapping problem is 1) fast and 2) precise in identifying the gate-level equivalents (the number of nets returned by our mapping engine for a query is typically one or two even for designs with tens of thousands of VHDL lines).

In this paper, we consider the mapping problem of identifying correspondences between a signal in a high-level specification and a net in a lower-level implementation for a given design. Conventional techniques use shared names to associate a signal with a net whenever possible. However, given that a synthesis flow may not preserve names, solutions to the above problem eventually take recourse to expensive alternatives such as formal verification. This paper provides a robust framework for identifying RTL signal to gate-level net correspondences for a given design. Our technique exploits the observation that circuit diagnosis provides a convenient means for locating faults in a gate-level network. Since our problem requires locating gate-level nets corresponding to RTL signals, we formulate the mapping problem as a query whose solution is provided by a circuit diagnosis engine. Our experimental work with industrial designs for many mapping cases shows that our solution to the mapping problem is (i) fast, and (ii) precise in identifying the gate-level equivalents (the number of nets returned by our mapping engine for a query is typically or 2 even for designs with tens of thousands of VHDL lines).

Improvement of the accuracy of error and fault diagnosis as well as ATPG for IP-based designs are important problems in industry. In this paper we address these problems when portions of the design may be unspecified. Two approaches to solve these problems have been presented: (1) solving Boolean satisfiability under unknown constraints, and (2) a network modification-based solution. Experimental results on constrained equivalence checking, enhancement of error diagnosis resolution for combinational circuits, and ATPG for IP-based designs have been presented on the ISCAS 85 benchmark and industrial circuits.

In this paper, we present multiple error diagnosis algorithms to overcome two significant problems associated with current error diagnosis techniques targeting large circuits: their use of limited error models and a lack of solutions that scale well for multiple errors.Our solution is based on a nonenumerative analysis technique, based on logic simulation (3-valued and symbolic), for simultaneously analyzing all possible errors at sets of nodes in the circuit.Error models are introduced in order to address the "locality" aspect of error location and to identify sets of nodes that are "local" with respect to each other.Theoretical results are provided to guarantee the diagnosis of modeled errors and robust diagnosis approaches are shown to address the cases when errors do not correspond to the modeled types.Experimental results on benchmark circuits demonstrate accurate and extremely rapid location of errors of large multiplicity.

Efficient identification of fault equivalence is essential for the completeness and efficiency of diagnostic test pattern generation. In this paper, we present new techniques to prove diagnostic fault equivalence. The techniques are based on implication of the faulty values, and functional evaluation at the dominator gate of the fault sites. The experimental results for all ISCAS85 circuits and full scan versions of ISCAS89 circuits show significant improvement compared to previously proposed techniques in both the number of equivalent pairs identified and the time to prove equivalence.

Efficient methods to evaluate the quality of a test set in terms of its coverage of arbitrary defects in a circuit are presented. Our techniques rapidly estimate arbitrary defect coverage because they are independent of specific, physical, fault models. We overcome the potentially explosive computational requirements associated with considering all possible defects by implicitly evaluating multiple faults (of all types) simultaneously and by exploiting the local nature of defects. Our experiments show that a strong correlation exists between stuck-at fault coverage and defects whose behavior is independent of the input vectors. Our techniques are capable of identifying regions in the circuit where defects may escape the test set. We also demonstrate how the chances of detection of an arbitrary defect by a test set vary when a single stuck-at-fault within the vicinity of that defect is detected multiple times by the test set.

In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DAWG).Our improvements are achieved by developing results that permit dynamic, fully functional, collapsing of candidate faults.Fault collapsing permits the organization of faults into disjoint partitions based on the indistinguishability relation.These results are used to develop a diagnostic test pattern generation algorithm that has the same order of complexity as that of detection-oriented test generation (ATPG).Techniques to identify untestable faults, based on exploiting indistinguishability identification, are also presented.Experimental results are presented on the ISCAS S9 benchmark circuits.

In this paper, we provide techniques for fault and error diagnosis based on capturing unmodeled faulty behavior. We present a technique for capturing the effects of all possible faulty behaviors that can be generated from specific sets of nodes (called X-lists) in the circuit. Since all possible erroneous behaviors are captured, this provides a way for drawing powerful diagnostic inferences about the presence of faults at these sets of nodes when analyzing the observed faulty responses. We also present an efficient diagnosis algorithm that exploits the modeling of all possible behaviors and can be built in a framework of conventional test and simulation tools. Experimental results with numerous diagnosis experiments are then used to demonstrate that the techniques developed can indeed be used to achieve significant improvements in the accuracy of diagnosis.

A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at primary input in the modified circuit techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits. Speed-up of the diagnostic ATPG process is achieved by the identification of states that are impossible to justify with three-valued logic.

Integrated fault diagnosis techniques attempt to overcome the limitations associated with static (pre-computed information usage) and dynamic (run-time analysis) techniques by using a limited amount of pre-computed information and coupling this with simulation at diagnosis time, for rapid fault diagnosis. A significant problem with previous integrated techniques is that the pre-computed information is not targeted specifically toward reducing the run-time costs. We present a new approach to integrated fault diagnosis, by specifically creating the precomputed information to provide later savings in the simulation costs at diagnosis time. Experimental results on the ISCAS 85 and ISCAS 89 circuits illustrate the savings achieved by this technique.

State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (hip-hops) that are either difficult to set or unsettable. This is achieved by performing test generation on certain transformed circuits to identify state elements that are not settable to specific logic values. Two applications that benefit from this identification are sequential circuit test generation and partial scan design. The knowledge of the state space is shown to be useful in creating early backtracks in deterministic test generation. Partial scan selection is also shown to benefit from the knowledge of the difficult-to-set hip-hops. Experiments on the ISCAS89 circuits are presented to show the reduction in time for test generation and the improvements in the testability of the resulting partial scan circuits.

Selection of flip-flops that provide the best improvements in testability is a critical part of the partial scan design process. This paper describes a new technique for flip-flop selection that models the effect of scan in terms of the introduction of pseudo state transitions in the state transition graph. The identification of (desired) state transitions that provide for improved testability is based on an analysis of the known reachable states and desired states which ensure improved fault detection. Experiments are presented on the ISCAS 89 circuits to show significant improvements in the testability of the resulting partial scan design.

A significant problem with current diagnostic test generation techniques is the time spent in identifying diagnostic equivalences amongst fault pairs. Fault pair distance analysis is introduced in this paper to characterize diagnostically equivalent fault pairs and motivate local circuit transformations and structural analysis to identify equivalences in combinational circuits rapidly. Our results establish a connection between redundant faults and a specific class of diagnostically equivalent fault pairs. Structural analysis is then used to identify equivalences between fault pairs. Experimental results are presented on benchmark circuits to demonstrate the efficiency of the techniques.

The process of fault dictionary compaction can lead to a loss of information that is potentially useful in locating unmodeled failures. The focus of this paper is on developing alternative storage structures that can efficiently represent full fault dictionaries without discarding any information. We present the problem of storing the full fault dictionary storage as a labeled tree encoding problem. Two labeled trees are introduced to represent the diagnostic experiment. For the first tree, the unlabeled tree is stored using a binary string code, while the second tree is constructed so that the unlabeled tree is regular in structure, thus allowing implicit storage. Eight alternative representations based on the three label components are presented and two existing full fault dictionary representations (the matrix and the list dictionaries) are shown to be special cases in our general framework. Experimental results on the ISCAS 85 and ISCAS 89 circuits are used to study and characterize the performance of the proposed storage structures.