Reliability of embedded memory is critical for system-on-chips (SoCs). Aging-induced faults manifest in field, and they affect the reliability of embedded memories which occupy the most area of an SoC. By performing a proactive approach that repairs aged memory words in use, the probability of fault occurrence should be minimized. In this paper, we proposed an in-field strategy that proactively repairs aged words as well as correctable words. The reliability is enhanced further by combining an aging test, an in-field repair, and an error correction technique. An adaptive reconfiguration of the memory words, including aged words, correctable words, and uncorrectable words, is implemented with small overhead. A 3-state model that identifies memory cells as healthy, aged, or faulty is newly introduced, and the reliability evaluation using this model demonstrates the effectiveness of the proposed strategy.

An on-chip digital sensor using three types of ring oscillators (ROs: Ring Oscillators) has been proposed to measure temperature and voltage of a VLSI. Each RO has inherent frequency characteristics with respect to temperature and voltage, which differ from those of the other two ROs. Measurement accuracy of the sensor depends on the combination of the ROs. This paper proposes a RO-selection method for the sensor with high accuracy. The proposed method takes particular note of temperature or voltage sensitivity as well as linearity of the RO characteristics. Evaluation experiments with SPICE simulation in 65 nm CMOS technology show that the temperature and voltage accuracies of the sensor are 2.744 °C and 3.825 mV, respectively, and the selected combination was a nearly optimal from a menu of many different ROs.

Avoidance of delay-related failures due to aging phenomena is an important issue of current VLSI systems. Delay measurement in field is effective for detection of aging-induced delay increase. This paper proposes a delay measurement method using BIST (Built-In Self-Test) in an FPGA. The proposed method consists of variable test timing generation using an embedded PLL, BIST-based delay measurement, and correction of the measured delay with reflecting temperature variance in field. In on-chip delay measurement of the proposed method, the fastest operating speed is checked by repeating delay test with several test timings. Because circuit delay is influenced by temperature during measurement, the measured delay is then corrected according to the temperature during testing. Based on test log including the corrected delay, delay degradation and aging detection can be grasped. In evaluation experiments of the propose method implemented on an Intel Cyclone IV FPGA device (60nm technology), variable test timing generation realized 96 ps timing step resolution (that is below 1% of the system clock), correction process for measured delay could reduce influence of temperature variation. Furthermore, its feasibility of the proposed method for aging detection is discussed in this paper.

Multi-cycle test with partial observation for scan-based logic BIST is known as one of effective methods to improve fault coverage without increase of test time. In the method, the selection of flip-flops for partial observation is critical to achieve high fault coverage with small area overhead. This paper proposes a selection method under the limitation to a number of flip-flops. The method consists of structural analysis of CUT and logic simulation of test vectors, therefore, it provides an easy implementation and a good scalability. Experimental results on benchmark circuits show that the method obtains higher fault coverage with less area overhead than the original method. Also the relation between the number of selected flip-flops and fault coverage is investigated.

This paper proposes a test cost reduction method using machine learning techniques. The proposed method tries to predict good dies among the manufactured dies on the way of test process. If a die is predicted as good before completing all of the test process, the die will be allowed to be shipped without going through the remaining test process which contains costly burn-in test and final test. By a SVM-based procedure together with K-fold cross validation, a prediction model to judge certainly good dies is created from known results of the selected test items. In order to evaluate the method in terms of the business effectiveness, we also propose new evaluation measures, "cost reduction rate" and "bad die escape rate", which enable to confirm zero-defect oriented test cost reduction. Experimental results obtained through test data for industrial dies requiring zero-defect show that the proposed method has significant predictability with high test cost reduction capability.

The proposed digital sensor measures both temperature and voltage simultaneously in field. The sensor is ring oscillator (RO)-based and its design is fully digital. Its measurement time is shorter than the conventional analog sensors' and it can be placed at any place such as the boundary of a CPU core, GPU core, or Memory. This paper investigates the accuracy of the sensor derived from reduction of temporal and spatial variations. The variations are evaluated by the measurement of a fabricated test chip. When the measurement time is long like the analog sensors, the variations during measurement has a great influence on sensor' accuracy. The comprehensive evaluations show that the total measurement error is smaller than the analog sensors' and it implies the importance of real time and contiguous measurement.

High power dissipation during scan-based logic BIST is a crucial problem that leads to over-testing. Although controlling test power of a circuit under test (CUT) to an appropriate level is strongly required, it is not easy to control test power in BIST. This paper proposes a novel power controlling method to control the toggle rate of the patterns to an arbitrary level by modifying pseudo random patterns generated by a TPG (Test Pattern Generator) of logic BIST. While many approaches have been proposed to control the toggle rate of the patterns, the proposed approach can provide higher fault coverage. Experimental results show that the proposed approach can control toggle rates to a predetermined target level and modified patterns can achieve high fault coverage without increasing test time.

Reliability of memory is crucial to overall reliability of SoCs. In our previous work, we enhanced reliability through an adaptive combination of repair and memory word correction, however, it is restricted to the identification of faulty memory words. In this work, we enhance reliability further by considering identification of not only faulty words, but aged words as well. We propose a novel method that adaptively assigns aged and faulty words to functional repair or correction based on their vulnerabilities.

Measuring temperature and voltage (T&V) in a current VLSI is very important in guaranteeing its reliability, because a large variation of temperature or voltage in field will reduce a delay margin and makes the chip behavior unreliable. This paper proposes a novel method of T&V measurement, which can be used for variety of applications, such as field test, online test, or hot-spot monitoring. The method counts frequencies of more than one ring oscillator (RO), which composes an aging-tolerant monitor. Then, the T&V are derived from the frequencies using a multiple regression analysis. To improve the accuracy of measurement, three techniques of an optimal selection of RO types, their calibration, and hierarchical calculation are newly introduced. In order to make sure the proposed method, circuit simulation in 180-, 90-, and 45-nm CMOS technologies is performed. In the 180-nm CMOS technology, the temperature accuracy is within 0.99 °C, and the voltage accuracy is within 4.17 mV. Furthermore, some experimental results using fabricated test chips with 180-nm CMOS technology confirm its feasibility.

Embedded memory is extensively being used in SoCs, and is rapidly growing in size and density. To keep up with the development pace of nanoscale devices, enhancement methods for yield and reliability must overcome the barriers set forth by advent of new technology. To address the issue of reliability, periodic online field test and repair are implemented by using synergistic approach of employing redundancy and ECC to repair or correct both hard errors and soft errors. In this paper, an online remap strategy for memory repair, which ensures ‘fresh’ memory words are always used until the spare words run out, is proposed. The improvement of reliability for memory architectures and the area overhead introduced by the proposed scheme is evaluated.

An on-chip environment monitor that can estimate a chip temperature and a power supply voltage has been developed to assist accurate circuit delay measurement by field test. The monitor consists of digital circuits and satisfies several features desired for the field test. This paper describes the architecture of the monitor and how to estimate the temperature and voltage in field, and finally shows simulation and TEG results on estimation accuracy.

Field test is performed in diverse environments, in which temperature varies across a wide range. As temperature affects a circuit delay greatly, accurate temperature monitors are required. They should be placed at various locations on a chip including hot spots. This paper proposes a flexible ring-oscillator-based monitor that accurately measures voltage as well as temperature at the same time. The measurement accuracy was confirmed by circuit simulation for 180 nm, 90 nm and 45 nm technologies. An experiment using test chips with 180 nm technology shows its feasibility.

Ring Oscillators are used for variety of purposes to enhance reliability on LSIs or FPGAs. This paper introduces an aging-tolerant design structure of ring oscillators that are used in FPGAs. The structure is able to reduce NBTI-induced degradation in a ring oscillator's frequency by setting PMOS transistors of look-up tables in an off-state when the oscillator is not working. The evaluation of a variety of ring oscillators using Altera Cyclone IV device (60nm technology) shows that the proposed structure is capable of controlling degradation level as well as reducing more than 37% performance degradation compared to the conventional oscillators.

Electronic systems that consist of various LSIs require very high reliability in field, however, physical degradation phenomena such as NBTI (Negative Bias Temperature Instability) make it difficult to keep reliability in field only by conventional manufacturing-based LSI testing. This paper proposes a stochastic model for NBTI-induced degradation in field and analyzes the effects of parameters that affect LSI failure rate by simulation. Quantitative discussions show a guideline for reliable design and test.

The applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses for good chips. Different from conventional low-power BIST, this paper is the first that has explicitly focused on achieving capture power safety with a practical scheme called capture-power-safe BIST (CPS-BIST). The basic idea is to identify all possibly erroneous test responses and use the well-known technique of mask (partial-mask or full-mask) to block them from reaching the MISR. Experiments with large benchmark and industrial circuits show that CPS-BIST can achieve capture power safety with negligible impact on both test quality and area overhead.

Low-power test technology has been investigated deeply to achieve an accurate and efficient testing. Although many sophisticated methods are proposed for scan-test, there are not so many for logic BIST because of its uncontrollable randomness. However, logic BIST currently becomes vital for system debug or field test. This paper proposes a novel low power BIST technology that reduces shift-power by eliminating the specified high-frequency parts of vectors and also reduces capture power. The authors show that the proposed technology not only reduces test power but also keeps test coverage with little loss.

High test power in logic BIST is a serious problem not only for production test, but also for board test, system debug or field test. Many low power BIST approaches that focus on scan-shift power or capture power have been proposed. However, it is known that a half of scan-shift power is compensated by test responses, which is difficult to control in those approaches. This paper proposes a novel approach that directly reduces scan-out power by modifying some flip-flops' values in scan chains at the last capture. Experimental results show that the proposed method reduces scan-out power up to 30% with little loss of test coverage.

This paper proposes a novel technique to measure temperature and voltage on-chip in field test. It consists of three types of NBTI-tolerant ring oscillator and counters constructed with a standard cell library. Temperature and voltage are estimated with high accuracy and in a short time.

Although many electronic safety-related systems require very high reliability, it is becoming harder and harder to achieve it because of delay-related failures, which are caused by decreased noise margin. This paper describes a technology named DART and its implementation. The DART repeatedly measures the maximum delay of a circuit and the amount of degradation in field, in consequence, confirms the marginality of the circuit. The system employing the DART will be informed the significant reduction of delay margin in advance of a failure and be able to repair it at an appropriate time. The DART also equips a technique to improve the test coverage using the rotating test and a technique to consider the test environment such as temperature or voltage using novel ring-oscillator-based monitors. The authors applied the proposed technology to an industrial design and confirmed its effectiveness and availability with reasonable resources.

This paper presents a novel failure prediction technique that is applicable for system-on-chips (SoCs). Highly reliable systems such as automobiles, aircrafts, or medical equipments would not allow any interruptive erroneous responses during system operations, which might result in catastrophes. Therefore, we propose a failure prediction technique that can be applied during an idle time when a system is not working, such as power-on/-off time. To achieve high reliability in the field, the proposed technique should take into consideration various types of aging mechanisms and the testing environment of voltage and temperature which is uncontrollable in the field. Therefore, we propose: 1) an accurate delay measurement technique considering the variation due to voltage and temperature and 2) an adaptive test scheduling that gives more test chances to more probable degrading parts. Experimental results show the required memory space and area cost for implementing the proposed technique.

Field test for reliability is usually performed with small amount of memory resource, and it requires a new technique which might be somewhat different from the conventional manufacturing tests. This paper proposes a novel technique that improves fault coverage or reduces the number of test vectors that is needed for achieving the given fault coverage on scan-based BIST structure. We evaluate a multi-cycle test method that observes the values of partial flip-flops on a chip during capture-mode. The experimental result shows that the partial observation achieves fault coverage improvement with small hardware overhead than the full observation.

For accurate failure prediction, it is important to eliminate the environmental delay variations from the measure delays for capturing the actual delay shift caused by aging. This paper presents a novel test pattern optimization method to reduces spatial and temporal temperature variations during delay test.

The special session covers the following: programmability based approach to post-silicon debug and rectification; an EDA tool chain for soft-error tolerant VLSI design; accurate and efficient SoC field test for failure prediction.

NBTI, which is one of well-known aging phenomena, brings delay degradation in deep submicron VLSIs. In order to detect NBTI-induced delay faults, we need to estimate delay degradation and apply delay test for the circuit in the field. This paper discusses on estimation of NBTI-Induced delay degradation. We first analyze the effect of the delay degradation, and then give a procedure of path selection in which long paths after the delay degradation are selected for the delay test in the filed. Experimental results show that estimation of delay degradation significantly affects path selection, and accurate estimation is important for the test.

This paper presents a novel failure prediction testing technique that is applicable for system-on-chips (SoCs). Highly reliable systems such as automobiles, aircraft or medical equipments would not allow any interruptive erroneous responses during a system operation, which might result in catastrophe. Therefore, we propose a failure prediction delay testing technique that is applied during the time when the system is not working, such as power-on/-off times. To achieve high reliability in the field, the proposed technique should take into consideration various types of aging mechanisms. Since the testing environment of voltage and temperature is uncontrollable in the field, an accurate delay measurement considering the variation due to voltage and temperature should be developed. Moreover, we propose an adaptive test scheduling that gives more test chances to more possible degrading parts for improving detecting efficiency.

It is well known that the test mode exceeds the functional mode in power consumption, which is not uniformly distributed within the circuit. The non-uniformity in spatial power distribution may cause localized heating and temperature differences within the circuit. Since gate delay depends on junction temperature, thermal differences within the circuit may lead to erroneous pass or fail in at-speed testing. This paper first discusses the importance of spatial thermal uniformity for high quality and accurate at-speed testing. The paper also presents an X-filling technique that minimizes the spatial temperature variation within the circuit while preserving the overall circuit power consumption at low level. Experimental results show the effectiveness of the proposed method compared to the existing X-filling techniques.

The Test industry has come a long way over the past few decades. As a whole we have made great strides in the areas of:

We propose a dynamic test compaction procedure to generate high-quality test patterns for path delay faults. While the proposed procedure generates a compact two-pattern test set for paths selected by a path selection criterion, the generated test set would detect not only faults on the selected paths but also faults on many unselected paths. Hence both high test quality by detecting untargeted faults and test cost reduction by reducing test patterns can be achieved. Experimental results show that the proposed procedure could generate a compact test set that detect many untargeted path delay faults certainly, compared with the static test compaction method previously proposed (Kajihara et al., 2005).

In order to generate correct at-speed scan patterns, the effect of timing exceptions and constraints needs to be considered during test generation. A path-oriented approach to handle timing exception paths during at-speed ATPG has been presented in (Vorisek et al., 2006). The new method has been applied to and tested on many example circuits at Semiconductor Technology Academic Research (STARC). This paper presents a sample of these test cases, and illustrates how the proposed method generates correct-by-construction at-speed patterns on these circuits without pessimism

In this paper, a new ATPG methodology is proposed to improve the quality of test sets generated for detecting delay defects. This is achieved by integrating timing information, e.g. from standard delay format (SDF) files, into the ATPG tool. The timing information is used to guide the test generator to detect faults through the longest paths in order to improve the ability to detect small delay detects. To avoid propagating faults through similar paths repeatedly, a weighted random method is proposed to improve the path coverage during test generation. During fault simulation, a new fault-dropping criterion, named dropping based on slack margin (DSM), is proposed to facilitate the trade-off between the test set quality and the test pattern count. The quality of the generated test set is measured by two metrics: delay test coverage and SDQL. The experimental results show that significant test quality improvement is achieved when applying timing-aware ATPG with DSM to industrial designs

Diagnosis has become a crucial technology for early debugging and yield improvement. However, the conventional diagnosis methods are not good at locating the defects that are not precisely expressed only with logical fault models. In this paper, we propose a novel defect diagnosis methodology, which is based on the evaluation of defect behaviors using physical information. We examine suspected nodes' voltages by comparing with the observed responses of ATE. In the examination, we use "defect activation", which is an estimation method of defective nodes' voltages using physical information. Using this methodology, we introduce examples of diagnosis for open defects in a cell, and for interconnect open defects. Those successful results show the effectiveness of the defect diagnosis

Assessing the effectiveness of transition fault testing by the test coverage is misleading and can result on lower product quality. In reality, the actual timing of the test for each fault determines if a delay defect of a given size is detected or not. Transition tests that use actual circuit timings to create tests with the tightest possible timing detect more defects and have higher test effectiveness for a given test coverage. This paper validates this assertion using a statistical delay quality model (SDQM) model to estimate the statistical delay quality level (SDQL) of several chips. The comparison includes transition tests generated with and without actual circuit timing as a function of the actual timing of the tests for each fault

The progress of design and fabrication technologies has led to an increase in small delay failures in systems-on-a-chip. To evaluate the delay testing quality accurately, the authors have already proposed a statistical approach that calculates actual sensitized path lengths that detect small delay defects in the transition delay test. However, the calculation requires a huge amount of CPU time. This paper presents a much more efficient method to calculate the sensitized longest path lengths and experimental results regarding CPU time and accuracy. The experiments show that this calculation method has high speed and high accuracy

This paper presents a framework of high-quality test generation for transition faults in full scan circuits. This work assumes a restricted broad-side testing as a test application method for two-pattern tests where control of primary inputs and observation of primary outputs are restricted. Because we use a modified time expansion model of a circuit-under-test during ATPG and fault simulation, conventional ATPG and fault simulation programs can work with minor change. The proposed ATPG method consists of two algorithms, which are activation-first and propagation-first, and for each fault it is decided which algorithm should be applied. Test patterns are generated such that transition faults with small delay can be detected, i.e. a path for fault excitation and propagation becomes as long as possible. In experimental results we evaluate test patterns generated by the proposed method using SDQM that calculates delay test quality, and show the effectiveness of the proposed method

In this paper we introduce a quality model that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that can predict the level of chip defects that cause delay failure, including marginal delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model.

In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths selected with a criterion. While the proposed method generates each two-pattern test for more than one fault in the target fault list as well as ordinary test compaction methods, secondary target faults are selected from the fault list such that many other faults, which may not be included in the fault list, are detected by the test pattern. Even if faults on long paths in a manufactured circuit are not included in the fault list due to a process variation or noise, the compact test set would detect the longer untargeted faults, i.e., the test set has a noise or variation tolerant nature. Experimental results show that the proposed method can generate a compact test set and it detects longer untargeted path delay faults efficiently.

The quality of delay testing focused on small delay defects is not clear when traditional fault models are used. We therefore evaluated the feasibility of using the statistical delay quality model (SDQM) - which reflects fabrication process quality, design delay quality, test timing accuracy, and test pattern quality - by using a commercial automatic test program generation (ATPG) tool to apply it to a large data set. The SDQM can also provide a measure predicting the defect level of a chip, and by simulating test patterns we show experimentally here that this measure can be calculated within a reasonable CPU time when using a reasonable amount of memory. Because we found when using SDF information to calculate path lengths accurately that the transition test patterns are not good at detecting small delay defects in long paths, a new test algorithm that detects small delay defects should be developed

Logic BIST is well known as an effective method for low cost testing. However, it is difficult to realize at-speed testing, as it requires a deliberate timing design in regard to logic design and layout of the chip. This paper presents a timing design methodology for at-speed BIST, using a multiple-clock domain scheme. Some experimental test results of large industrial designs using our custom fool "Singen", will also be shown.

This paper presents an at-speed built-in test method for logic circuits with multiple clocks. It is clear that BIST (built-in self-test) plays a key role in test strategy for SoCs. It is also obvious that at-speed BIST is necessary for high quality test. Though several approaches enable at-speed BIST, there still exist several issues, such as multiple clocks, multi-cycle transfers and false paths. The proposed method realizes at-speed test for arbitrary combination of release and capture clocks at reasonable test time by utilizing the LFSR reseeding technique. Experimental results for benchmark circuits and an industrial circuit are given to illustrate the effectiveness of our approach.

This paper presents an approach for high-quality built-in test using a neighborhood pattern generator (NPG). The proposed NPG is practically acceptable because (a) its structure is independent of circuit under test, (b) it requires low area overhead and no performance degradation, and (c) it can encode deterministic test cubes, not only for stuck-at faults but also transition faults, with high probability. Experimental results for large industrial circuits illustrate the efficiency of the proposed approach.

We present a persistent diagnostic technique for unstable defects, such as open defects or delay defects. A new "segment model" diagnosis for the completely open defects is discussed. Here, we not only focus on the behavior of the principal offender, but also the behavior of the accomplices which cause the unstable behavior of the defect. In this paper, a technique using the layout information for an open fault diagnosis, and a testing method for the delay fault are discussed. Some experimental results of actual chips are shown.

Presents a practical coverage metric in delay testing, which is called a multiple-threshold gate-delay fault model, to obtain high quality tests for large circuits. Fault efficiencies for given multiple thresholds of the delay fault size are computed, and their entirety describes the quality of tests. The approach guarantees that each gate-delay fault is not only robustly tested on almost the longest path, but also tested under the condition as a transition fault, by using two-pattern tests with a pattern-independent timing. We present procedures of path selection, fault simulation and test generation, where the path-status graph technique is used for an efficient computation. Experimental results for industrial circuits demonstrate that the proposed method can achieve high fault efficiencies for gate-delay faults having various fault sizes in a practical processing time.

Increasing number of pins or gates in the latest LSIs requires a lot of testing resources. The conventional scan-based testing requires a costly tester (ATE) equipped with a lot of pin electronics. Since reducing the testing cost is a crucial issue in industry, we have introduced an approach using scan-based logic BIST to solve this problem. The logic BIST has been applied to many ASIC design chips, which have up to several million gates.

Presents a practical approach to improve the resolution of defect-based diagnosis. To diagnose the faulty chips, various techniques are needed as well as modeling the defects precisely. In this paper, some techniques using the layout information, a multi-test diagnosis method, and a testing method for the delay fault are discussed, and some experimental results of actual chips are shown. The resolution of the diagnosing test patterns is also discussed.

This paper presents an evaluation of defect-oriented test that targets bridging defects or leakage defects in the deep sub-micron process. As the power supply voltage or the threshold voltage (Vt) decreases, the detection of these defects becomes more difficult. Therefore the effectiveness of each test method should be clarified. In this paper we newly propose the WELL-controlled low voltage (WLV) test, which is a low-voltage test with substrate back biasing, and prove that it detects the defects that are not detected by the IDDQ test. The effectiveness of the WLV test for a small gate-width circuit is also discussed for a noisy environment when the very-low-voltage (VLV) test is inapplicable.

This paper presents a BIST approach for the very deep submicron (VDSM) defects in an ASIC. As bridging or open defects are dominant in VDSM, efficient and accurate tests to detect them are now strongly required. We evaluated the BIST patterns for various criteria. These evaluations and additional real chip experiments have indicated that BIST has better detectability of defects than the conventional stored test.

This paper considers distributed algorithms for distributed mobile systems. Many distributed algorithms have been designed for distributed systems consisting of static computers only. But most of them cannot be directly applied to mobile systems. This paper proposes a model of mobile systems. Management of movements of mobile hosts is abstracted in our model to simplify design of algorithms for mobile systems. This paper also defines the snapshot problem, one of the fundamental problems, on the model. The problem requires to find a strongly consistent configuration in which topological consistency is satisfied in addition to causal consistency. Furthermore, this paper presents a snapshot algorithm for mobile systems.

Timing-and constraint-oriented placement procedures are

This paper proposes a new method for connected word recognition. To reduce pattern matching errors which are caused by coarticulation, talking rate variation, and silence between words in continuous speech, overlap and splitting of reference patterns and normalization of accumulated distances are introduced into our basic recognition algorithm. Also new algorithms to reduce the amount of computation and to train the recognition system are proposed. Performance evaluation tests show the efficiency of these algorithms and the entire method. Dominant factors of speech data influencing recognition performance are also investigated.

A system is proposed for automatic speech recognition using syllable templates. In this system, input speech signal is analyzed and matched against syllable templates and converted into parameters characterizing each candidate syllable. Word recognition is based on an overall likelihood measure calculated for each item stored in the lexicon. A method is also developed for the optimization of syllable templates. The validity of the proposed method was tested in a preliminary recognition experiment in which a lexicon consisting of 1000 city names was used to recognize utterances of 100 city names by a female speaker. The rate of correct recognition was 96.5%.

In spite of its extensive use, speech analysis based on linear prediction (LP) is liable to various causes of inaccuracy. This paper presents a novel approach to improve the accuracy in the estimation of the voiced speech production model based on the LP method. The presented method uses interpolation between spectral points which are least influenced by artifacts in the spectral analysis and by noise in the signal. We show, on analyses of both synthetic and natural speech, that the averaged parabolic approximation between harmonic peaks of voiced speech spectrum reduces the sensitivity of the LP analysis to changes in the fundamental frequency Fo and to noise. The method is well suited for combination with the Spectral Transform LP method, previously proposed by the authors [1].

The Linear Predictive (LP) method has been widely used in speech analysis, mainly because of the simple mathematical formulation of the model and the straightforward computation of its parameters. However, there still remain certain difficulties that cause errors in the result of the analysis. Often encountered are the errors due to harmonic structure of the excitation source. The Spectral Transform LP (STLP) method proposed in the present paper aims at reducing these errors. Amplitude transforms on the input spectrum and on the spectrum of the model are introduced to modify the error criterion and the model adopted in the standard LP analysis. We show by analyses of both synthetic and natural speech that the STLP method offers significant improvement over the standard LP method. A method of STLP speech synthesis using the standard LP model is proposed. A perceptual experiment confirms the superiority of the STLP method in analysis of speech.