In order to protect public network data transmission from potential Layer 1 attacks by malicious users, self-synchronous scramblers have come into widespread use. Such networks include those using ATM, packet over SONET (POS), and the new generic framing procedure (GFP). Unfortunately, feedback taps inherent in self-synchronous descramblers cause multiplication of transmission errors, which in turn degrades the performance of most linear cyclic error detection/correction codes. This paper analyzes this scrambler/code interaction with respect to the resulting probability of undetectable errors and transmission error correction capability. The theoretical criteria are derived for a linear cyclic code to maintain its error detection and correction performance in the presence of the scramblers. A novel approach for improving the error correction capabilities is also presented.

In order to protect public network data transmission from layer 1 attacks by malicious users, self-synchronous scramblers have come into widespread use. Such networks include those using ATM, packet over SONET (POS), and the new generic framing procedure (GFP). Unfortunately, self-synchronous descramblers cause error multiplication that can degrade the performance of the popular CRC error check codes. The paper analyzes this scrambler/CRC interaction, and then presents a new class of CRC-16 codes that are optimized for these applications.

Broadband integrated services digital networks (B-ISDN), which utilize asynchronous transfer mode (ATM) technology, promise to provide a common platform for greatly increased service capacity. In terms of virtual path (VP) protection switching time, a high-bandwidth VP should be switched faster than a low-bandwidth VP in order to keep the number of damaged cells proportional to the total number of cells in that VP. This paper proposes a notification method using user cells. The proposed method can notify without interrupting the existing user cells. The total switching times were measured experimentally as 1 msec for 1.5 Mbps and 100 /spl mu/sec for 15 Mbps. These results demonstrate that the bandwidth adaptive method is very fast compared to VP AIS methods, and even STM methods which require 50 msec.

The coded mark inversion (CMI) line code is becoming popular for wide-band fiber-optic systems. The advantages of the CMI include DC balance and guaranteed transition density, which simplifies timing recovery. Previous CMI encoder implementations typically relied on a mixture of digital, analog, and delay-line techniques. The encoders proposed are digital state machines that allow elegant, accurate, and efficient implementation with gate arrays or discrete logic components. A general approach is then discussed for designing state machines of the type described here. Such state machines may be used to implement other codes, such as Manchester, RZ, and BnZS codes.

Recently, a self-testing ALU design has been proposed that uses Berger codes and compares the check value of the ALU output to a predicted check value that is calculated based on the input operand check values. Berger codes have the property of being able to detect all unidirectional errors. More efficient codes exist for detecting up to t unidirectional errors. This paper examines applying these codes to self-testing ALU designs and shows that the potential savings in check circuitry over Berger codes is up to 61%, depending on the code and the information word length.