This paper aims at presenting how new technologies can overcome classical implementation issues of Neural Networks. Resistive memories such as Phase Change Memories and Conductive-Bridge RAM can be used for obtaining low-area synapses thanks to programmable resistance also called Memristors. Similarly, the high capacitance of Through Silicon Vias can be used to greatly improve analog neurons and reduce their area. The very same devices can also be used for improving connectivity of Neural Networks as demonstrated by an application. Finally, some perspectives are given on the usage of 3D monolithic integration for better exploiting the third dimension and thus obtaining systems closer to the brain.

Motivated by energy constraints, future heterogeneous multi-cores may contain a variety of accelerators, each targeting a subset of the application spectrum. Beyond energy, the growing number of faults steers accelerator research towards fault-tolerant accelerators.

In order to cope with increasingly stringent power and variability constraints, architects need to investigate alternative paradigms. Neuromorphic architectures are increasingly considered (especially spike-based neurons) because of their inherent robustness and their energy efficiency. Yet, they have two limitations: the massive parallelism among neurons is hampered by 2D planar circuits, and the most cost-effective hardware neurons are analog implementations that require large capacitors, We show that 3D stacking with Through-Silicon-Vias applied to neuromorphic architectures can solve both issues: not only by providing massive parallelism between layers, but also by turning the parasitic capacitances of TSVs into useful capacitive storage.

Neuromorphic circuits aim at emulating biological spiking neurons in silicon hardware. Neurons can be implemented either as analog or digital components. While the respective advantages of each approach are well known, i.e., digital designs are more simple but analog neurons are more energy efficient, there exists no clear and precise quantitative comparison of both designs. In this paper, we compare the digital and analog implementations of the same Leaky Integrate-and-Fire neuron model at the same technology node (CMOS 65 nm) with the same level of performance (SNR and maximum spiking rate), in terms of area and energy. We show that the analog implementation requires 5 times less area, and consumes 20 times less energy than the digital design. As a result, the analog neuron, in spite of its greater design complexity, is a serious contender for future large-scale silicon neural systems.

The conduction delay in neural systems has been proven to play an important role in processing neural information. In hardware spiking neural networks (SNN), emulating conduction delays consists of intercepting and buffering spikes for a certain amount of time during their transfer. The complexity of the conduction delay implementation increases with high spiking rates; it implies (1) storing a large number of spikes into memory cells and (2) conserving the required time resolution while processing the delays. As a result, the circuit size becomes very large and difficult to integrate into large scale SNN systems. In this paper, we highlight the trade-offs of an efficient digital delay circuit design supporting high neuron firing rates. The key issue resides in conserving spikes and spike timings while limiting storage requirements. We present a digital implementation of a configurable delay circuit supporting spiking rates of up to 1Meps (Mega events per second) and a delay range going from 1μ with a time resolution less than 5% of the configured delay time. Synthesis results show that, using the CMOS 65nm technology, the required silicon area is 1600μm2.

Because of power and reliability issues, computer architects are forced to explore new types of architectures, such as heterogeneous systems embedding hardware accelerators. Neuromorphic systems are good candidate accelerators that can perform efficient and robust computing for certain classes of applications. We propose a piking neurons based accelerator, with its hardware and software, that can be easily programmed to execute a wide range of signal processing applications. A library of operators is built to facilitate implementation of various types of applications. Automated placement and routing software tools are used to map these applications onto the hardware. Altogether, this system aims at providing to the user a simple way to implement signal processing tasks on neuromorphic hardware.

Closed-loop operation of a brain-machine interface (BMI) relies on the subject's ability to learn an inverse transformation of the plant to be controlled. In this paper, we propose a model of the learning process that undergoes closed-loop BMI operation. We first explore the properties of the model and show that it is able to learn an inverse model of the controlled plant. Then, we compare the model predictions to actual experimental neural and behavioral data from nonhuman primates operating a BMI, which demonstrate high accordance of the model with the experimental data. Applying tools from control theory to this learning model will help in the design of a new generation of neural information decoders which will maximize learning speed for BMI users.

Brain-machine interfaces (BMIs) provide a versatile tool for rehabilitation of severely disabled people. Current BMI systems focus on the control of kinematic variables. However, this approach limits the application space of BMI technology to simulated environments. Real-world rehabilitation robots, on the other hand, must operate in a variety of complex physical situations. BMI systems that are aimed toward prostheses must, then, control interaction forces with their environments. In this paper, we design a BMI-driven architecture that provides a critical link between neuronal ensemble activity and real-world dynamics. In particular, our system allows simultaneous estimation of kinematic and stiffness variables of a prosthetic device. This approach is achieved by recording instantaneous activities from cortical neural ensembles that input to a musculoskeletal model of the arm, from which limb kinematics and dynamics are estimated and converted into control signals of a prosthetic device. Using real neural and behavioral data from nonhuman primates, we show that our architecture can accurately predict kinematic and stiffness variables in different dynamic situations. This architecture has strong implications in the development of the next generation of neural prosthetics that will restore motor function in neurologically impaired patients. Moreover, it demonstrates a novel framework for studying how the brain learns and adapts to new environments.

This paper presents a model of the learning process occurring during operation of a closed-loop brain-machine interface (BMI). The learning model updates neuron firing properties based on a feedback-error learning scheme, featuring feedforward and feedback controllers. Our goal is to replicate in simulation experimental results showing functional reorganization of neuronal ensembles during BMI experiments. We show that the proposed model can simulate motor learning, and that the predicted changes in neuronal tuning are consistent with experimental observations. We believe that being able to simulate motor learning in a BMI context will allow designing decoders that would facilitate the learning process in real world experiments.

This paper describes a method for providing in real time a reliable synchronization signal for cyclical motions such as steady-state walking. The approach consists in estimating online a phase variable on the basis of several implicit central pattern generator associated with a set of sensors. These sensors can be of any kind, provided their output strongly reflects the timed motion of a link. They can be, for example, spatial position or orientation sensors, or foot sole pressure sensors. The principle of the method is to use their outputs as inputs to nonlinear observers of modified Van der Pol oscillators that provide us with several independent estimations of the overall phase of the system. These estimations are then combined within a dynamical filter constituted of a Hopf oscillator. The resulting phase is a reliable indexing of the cyclic behavior of the system, which can finally be used as input to low-level controllers of a robot. Some results illustrate the efficiency of the approach, which can be used to control robots.