This paper addresses the software transformation part of a comprehensive hardware/software co-design flow for the Discrete Event System Specification Model of Computation. The transformation methodology of such timed abstract models into embedded systems source code is the main contribution of this paper. Furthermore, the integration of legacy source code and communication interface instantiation is detailed. Thus, the advocated approach allows to reuse legacy source code within a hardware/software co-design flow based on model transformations. The feasibility of the approach is demonstrated by means of a realistic distributed real-time application example.

This paper presents a state optimization approach within the Discrete Event System Specification Model of Computation. The goal of state optimization is to significantly soften the timing requirements of the model when transformed to a hardware implementation. The algorithm presented relocates the behaviour of zero-timeout states into adjacent states. Thus, the resulting model has much better timing properties, which considerably increase the amount of suitable target hardware architectures. The feasibility of the approach is demonstrated by means of a complex Digital Visual Interface controller application example.

The McEliece public-key cryptosystem relies on the NP-hard decoding problem, and therefore, is regarded as a solution for postquantum cryptography. Though early known, this cryptosystem was not employed so far because of efficiency questions regarding performance and communication overhead. This paper presents a novel processor architecture as a high-performance platform to execute key generation, encryption, and decryption according to this cryptosystem. A prototype of this processor is realized on a reconfigurable device and tested via a dedicated software interface. A comparison with a similar software solution highlights the performance advantage of the proposed hardware solution.

McEliece scheme represents a code-based public-key cryptosystem. So far, this cryptosystem was not employed because of efficiency questions regarding performance and communication overhead.This paper presents a novel processor architecture as a high-performance platform to execute key generation, encryption and decryption according to this cryptosystem. A prototype of this processor is realized on Virtex-5 FPGA and tested via a software API. A comparison with a similar software solution highlights the performance advantage of the proposed hardware solution.

This paper describes a systematic approach to integrate the Discrete Event Specified System (DEVS) methodology into SystemC. It thus combines Model of Computation (MoC) specific properties and the features of an advanced SystemC environment. The execution of abstract system level DEVS models is comparable to pure SystemC models and is significantly faster compared to other DEVS environments. Thus, system level models based on abstract MoCs may easily be executed in a SystemC environment. The proposed integration is realized as a non-introspective extension to the SystemC 2.2 kernel. The DEVS models are implemented on an additional software layer above the SystemC simulation kernel. Our approach may be used simultaneously with other layered extensions, e.g., SystemC-AMS or TLM.