This live demonstration shows a mixed-signal design in 180 nm CMOS technology that runs hyperdimensional computing (HDC) on binary hypervectors with up to 8,192 components. The chip comprises 64 × 128 processing elements (PE) arranged in a 2D mesh with direct connection to their first neighbors. PEs include a 1-bit ALU with a 16 6T-SRAM bank to execute HDC primitives. Hypervector classification is performed through the Hamming distance with current sources in every PE globally connected to an analog computing unit laid down outside the PE array. The overall approach results in tens of nJ of power consumption in inference, which is competitive with state-of-the-art solutions.

This live demonstration shows a mixed-signal Computer In Memory (CIM) macro deep neural network (DNN) integrated circuit in 180 nm CMOS technology for image recognition. Images are coded as pulse width modulation (PWM) signals. DNN weights are stored as voltages in 6T-SRAM memories which drive current sources inside every multiplier. Multipliers are arranged within processing elements laid down in a 2D mesh suitable for image processing. The power consumption per multiplier of the CIM macro is of 0.22 µW, below state-of-the-art competitors following the same multiply and accumulate (MAC) principle.

This paper explores the feasibility of a capacitor-less (CL) low-dropout (LDO) regulator to operate efficiently in a low-voltage environment. The CL-LDO scheme selected is based on a unity-gain feedback configuration around the error amplifier (EA), so that the inclusion of high-value on-chip resistors is avoided and different key parameters, such as the power supply rejection or the noise, are optimized. A comparative analysis has been carried out over the same LDO structure including a bulk-driven and a gate-driven EA, respectively. The pass branch of the voltage regulator is provided with pseudo-class-AB operation, in order to lead to a very small quiescent current in the standby operation mode, whereas a very large current can be delivered to the load when required. Both regulators were designed and fabricated in 180 nm CMOS technology to operate with a maximum supply voltage of 1.8 V. The extensive experimental characterization showed that the bulk-driven LDO can achieve a significantly lower minimum supply voltage, i.e., 0.6 V, as compared to the gate-driven counterpart, 1 V, under the same reference voltage and load current conditions.

A subthreshold input voltage charge pump based on the well-known cross-coupled voltage doubler and using boosted gate voltages for the transfer switches is presented. A level shifter and some inverters, including a novel inverter architecture proposed in this work and referred to as negative low-state voltage inverter, are used to generate the clock signals for the switching transistors with the purpose of significantly improving their drive capability. A complete analysis of the proposed charge pump is provided to highlight the advantages of the implemented structure, revealing the power efficiency improvement when the input voltage is below the threshold voltage of the transistors. An extensive experimental characterization of silicon prototypes in 180 nm CMOS technology was carried out, showing that the proposed scheme is able to pump charge from an input voltage as low as 110 mV. The experimental peak efficiency remains above 70% for input voltages between 180 mV and 400 mV and input power levels from 45 nW to 25$\mu \text{W}$, which are appropriate for different miniaturized transducers implementable on chip.

This paper addresses a mixed-mode CMOS circuit for Hyperdimensional Computing (HDC). HDC is based on the use of binary vectors with thousands dimensions to represent data in a holistic way. During the last years HDC has shown to be a powerful approach to solve classification problems. The proposed circuit architecture in this paper is made up of an array of 128 × 64 (8192) processing units (PUs) with a 1-bit ALU, local memory and connectivity to their 4 nearest neighbors to run the basic operations of HDC, i.e, binding, bundling and permutation. The architecture also includes a module to calculate Hamming distance to address classification. Post-layout simulations of the complete system working on various basic operations in 0.18 μ m CMOS technology are shown.

Neural network mixed-mode hardware accelerators for deep convolutional neural networks (CNN) strive to cope with a high number of input feature maps and increasing bit depths for both weights and inputs. As an example of this need, the ResNet model for image classification comprises 512 3× 3 feature filters in its conv5 layer. This would lead to 4068 multipliers driving a summing node for actual concurrent processing of all the input feature maps, which makes up a challenge in mixed-mode. This paper addresses the design of a 5-bit signed SRAM-based in-memory computing cell in 180 nm 3.3 V CMOS technology, dealing with the impact of increasing the number of input feature maps. The data presented in the paper are based on electrical and post layout simulations.

Indirect time of flight (IToF) allows for accurately retrieving 3D geometry without the need for exorbitant time resolution. Nevertheless, the use of continuous-wave (CW) periodic modulation brings the need for multiple frequency measurements to solve depth ambiguities or cope with multi-path interference. Sequential acquisition of multiple frames reduces the frame rate, while harmonic distortion of the modulation waveforms produces wiggling in the depth estimation. This paper presents and verifies the operation of an IToF CMOS image sensor designed to provide single-shot multi-frequency measurements. A macro-pixel structure allows acquiring multi-frame data in one shot, while resonant demodulation annihilates the harmonic content. The novel architecture consists of 10 $\mu m \times 10 \mu m$ 2 -tap pixels with a 20% fill factor (FF). Post-layout simulations show promising 3D reconstruction for up to 16 different simultaneous frequencies.

A capacitor-less (CL) low-dropout (LDO) regulator suitable to be incorporated in an on-chip system with low-voltage micro-energy-harvested supply, is proposed in this contribution. The differential input stage of the error amplifier includes bulk-driven MOS transistors, thus providing the LDO with an output voltage range that extends from the negative rail up to a level very close to the input voltage without the need of using a resistive feedback network. The circuit parameters relying on the feedback factor,$\beta $, are maximized thanks to the use of a unitary value for this parameter. The CL-LDO has been designed and fabricated in standard 180-nm CMOS technology and optimized to operate with an input voltage equal to 0.6 V and a reference level of 0.5 V. The experimental characterization of the fabricated prototypes shows that, under these operating conditions, the LDO is able to deliver a load current above 0.75 mA with a total quiescent current of only 7.0 nA. Furthermore, the proposed voltage regulator is able to operate from input voltages as low as 0.4 V, delivering in this case a maximum load current of 30$\mu \text{A}$.

“Fail often to succeed sooner” is a common mantra that we are told is the secret to success. When reporting research results, however, scholars rarely write about their failed attempts and only focus on the successful ones. Perhaps the source of this disconnect between what we preach and what we do can be found in the underlying assumption that published work is meant to move the field forward and failed attempts supposedly do not. The goal of the confessions presented in this paper is to show that even failed attempts are genuine and valuable contributions to our field provided that we learn from our mistakes and correct them. The 27 confessions span from planning oversights, digital and analog design errors, misunderstanding of devices, overlooked parasitics, LVS errors, and troubles in testing.

Background subtraction is one of the first steps in many video processing algorithms. Thus, a real-time processing with low power consumption is convenient for different applications where power hungry devices with high computational capabilities can not be deployed. This work presents the design of a 24×56 pixel proof-of-concept 0.18 μm standard CMOS vision sensor chip implementing the foreground detection algorithm Hardware Oriented Pixel Based Adaptive Segmenter (HO-PBAS) on the focal plane. Simulation results show a maximum processing speed of 2000 fps with a figure of merit of 1.3 μW/pixel at 60 fps and a pixel pitch of 47 μm in a four pixels per processing element configuration.

An ultra-low power LDO regulator with an adaptive biasing error amplifier is presented in this paper. An absolute difference voltage meter circuit section based on super source followers is used to achieve the adaptive biasing scheme. The experimental total quiescent current consumption is as low as 1.88 nA with a measured line sensitivity of 0.13 mV/V in a circuit occupying 1473 μm2of silicon area.

Multiple object visual tracking of real time detected objects using a low-power embedded solution is shown. The proposal is implemented on a NVIDIA Jetson TX2 development kit demonstrating the feasibility of deep learning techniques for IoT and mobile edge computing applications.

This paper presents a 1 mm2solar cell and a Power Management Unit (PMU) on the same substrate to rise up the harvested voltage above 1.1 V to power wearable or implantable devices. The on-chip solar cell and the PMU are fabricated in standard 0.18 μm CMOS technology achieving a form factor of 1.575 mm2. Experimental results show that the PMU is able to start-up from a harvested power of 2.38 nW without any external kick off or control signal and can handle a harvested power up to μW with a continuous and two-dimensional Maximum Power Point Tracking (MPPT) that works in open-loop mode to set the frequency, the gain and the capacitor sizes of a charge pump.

This paper presents an indirect Time-of-Flight sensor for standard CMOS technologies with an alternative demodulation scheme based on homodyne techniques. This avoids control signals shorter than the period of the emitted light signal, which prevents synchronization issues and minimizes switching effects like charge injection and clock feedthrough. The feasibility of the pixel and the demodulation scheme is demonstrated through simulations.

Compute and memory demands of state-of-the-art deep learning methods are still a shortcoming that must be addressed to make them useful at Internet of Things (IoT) end-nodes. In particular, recent results depict a hopeful prospect for image processing using convolutional neural networks, CNNs, but the gap between software and hardware implementations is already considerable for IoT and mobile edge computing applications due to their high power consumption. This proposal performs low-power and real time deep learning-based multiple object visual tracking implemented on an NVIDIA Jetson TX2 development kit. It includes a camera and wireless connection capability and it is battery powered for mobile and outdoor applications. A collection of representative sequences captured with the on-board camera, dETRUSC video dataset, is used to exemplify the performance of the proposed algorithm and to facilitate benchmarking. The results in terms of power consumption and frame rate demonstrate the feasibility of deep learning algorithms on embedded platforms although more effort in the joint algorithm and hardware design of CNNs is needed.

This live demonstration is related to ISCAS track “4.5: Circuits & Systems for Energy Harvesting”. This live demo shows a micro-energy harvesting system which includes a 1 mm2solar cell as the unique power source and a Power Management Unit (PMU) on the same substrate in standard 0.18 μm CMOS technology. The PMU has cold start-up from nW and it also performs a continuous and two-dimensional maximum power point tracking using analog strategies to meet very low power consumption, managing a high input power range. The system is used to power an off-chip NAND gate.

Foreground segmentation algorithms are sometimes provided with feedback mechanisms to deal with complex scenarios such as dynamic backgrounds. This is accomplished with background dynamic estimators in the case of foreground detectors based on non-parametric models with a historical record of the background. This work introduces the Shannon entropy as a new background dynamics estimator. The paper shows that this approach leads to better figures of merit than those provided by the original background dynamics estimators in state-of-the-art algorithms such as PBAS and SuBSENSE for complex scenarios as dynamic backgrounds or camera jitter in the database ChangeDetection. Also, the Shannon entropy permits to decrease the number of samples in the background model, cutting memory usage, and thus making implementations on embedded devices easier.

The high number of memory accesses in background subtraction algorithms constraints the choice of the memory topology of an analog implementation of a hardware-oriented version of the well-known PBAS algorithm (HO-PBAS). As the first step towards the implementation of a CMOS vision chip with per-pixel processing to run the HO-PBAS, this work assesses the impact of the circuit non-idealities of the three main analog memory topologies into the segmentation result on the CDNET database.

This paper presents a dynamic model for on-chip inverting capacitive charge pumps driven by two non-overlapping clock signals. The model implements the charge reusing technique to mitigate the efficiency loss due to the charge and discharge process of the parasitic capacitances. Validation with both circuit-level simulations and experimental results is shown, demonstrating high accuracy. An application example in micro energy harvesting is given.

This live demonstration is related to ISCAS track “Sensory Systems: Sensor Networks”. This live demo shows a wireless sensor network of custom-made differential capacitive sensors with the ZigBee protocol for snail pest detection. The wireless sensor network provides the snail occupation level of a given plantation area. Validation of the wireless sensor network in both controlled mini plots in a greenhouse and outdoor small areas has been made.

This paper introduces a Time-of-Flight sensor of 50 × 60 pixels in standard CMOS 0.18 μm technology with in-pixel adaptive number of accumulations and background suppression. Background suppression is carried out through two mechanisms, namely, the increase of signal to background ratio, and background subtraction. The pixel features a fill factor of 77% with an nwell over p-substrate diode of 50 × 50 μm2. The pixel senses the photocurrent through a transimpedance amplifier. Adaptive accumulations are performed with an in-pixel comparator that is also used for per-column A/D conversion as part of an 8-bit single-slope ADC. The sensor works with 4 square pulses of 50 ns. Simulations show that the chip could measure distances up to 7.5 m without optical filters for background levels up to 20 klux at video frame rate.

This paper studies the dark current (DC) of the photodiode (PD), the transmission gate (TG), and the floating diffusion (FD) in 4-Transistor (4T) pixels in standard CMOS technologies for Time-of-Flight (ToF) sensors through device simulations. The paper addresses the layout optimization in terms of DC for an nwell/psub and two custom pinned-photodiodes (PPD), stating their pros and cons.

This paper proposes a hardware implementation to speed up the calculation of the feature descriptor vector in the Scale-Invariant Feature Transform (SIFT) algorithm. The proposed architecture, which improves conventional solutions based on embedded processors or other hardware/software co-designs, computes a feature descriptor vector of 27 elements from a keypoint neighborhood of 15×15 pixels. This process comprises several steps, including complex operations such as vector normalization operations. The paper compares two different implementations: one being time-optimized and the other memory-optimized. Both approaches require 649 and 874 clock cycles respectively for a single feature vector calculation (6.49 μs and 8.74 μs for a 100 MHz FPGA).

The lateral collection capacity of small CMOS photodiodes, scanned with a point source illumination, is studied. The mathematical solution of the physical equations is compared to experimental measurements in a standard UMC 90nm technology. They show close agreement and reveal that the lateral collection through the sidewalls of the depletion region becomes a significant component of the overall photocurrent. The same conclusion is achieved through device simulations under uniform illumination using ATLAS.

Modelling of physical phenomena often involves the use of complex systems of equations whose computational solution has demanding requirements in terms of memory and computing power. Among the different techniques proposed, the Finite-Difference Time-Domain (FD-TD) method has the advantage of a feasible hardware implementation that can significantly speed up the computations. This technique is widely used for the solution of partial differential equations in a variety of areas such as antennas design, medical studies, circuit packaging and non-destructive evaluation. In this paper, we present a hardware accelerator of a 3D FD-TD heat equation solver that constitutes the basis of a thermal model of the soil for the non-destructive evaluation of minefields using infrared thermography techniques. In order to be able to work on the field during mine removal activities, a portable and computationally efficient system must be achieved. To this aim, we projected the 3D FD-TD model of the soil onto an FPGA platform using Handel-C and VHDL. A speedup factor of 34 over a single precision PC (C++) is achieved.

Modeling of physical phenomena often involves the use of complex sets of equations whose computational solution has demanding requirements in terms of memory and computing power. Finite-Difference Time-Domain (FD-TD) method is a technique widely used nowadays in a variety of areas, such as antennas design, medical studies, circuit packaging and non destructive evaluation (NDE), having the advantage of a feasible hardware implementation of the algorithm that can significantly speedup the computations. In this paper we will focus on the thermal modeling of the soil for NDE. To this aim we projected a true 3D FD-TD model of the soil on an FPGA. Two different implementations of the system were made, one developed with VHDL and another one with Handel-C. A speed-up factor of 160 over a PC is achieved which shows the utility of such an implementation.

Infrared thermography is a technique for the detection of plastic mines. Its application requires the solution of the equations that govern the heat transfer processes. We present an FPGA projection of a system that solves these equations

The use of infrared (IR) images of the soil is an efficient technique to detect shallowly buried landmines. The detection is possible due to the different thermal properties of the soil and the mine. The core of this technique is the simulation of the heat transfer processes in the soil and at the soil-air interface. Simulation of these processes is a very long-time consuming task on ordinary computers. Its execution on dedicated hardware can reduce the computing time. In this paper we show the architecture of a system that simulates the thermal processes onto an FPGA, showing the feasibility of such a realization.

In this paper, we address the problem of the detection and identification of surface-laid and shallowly buried landmines from measured infrared images. A three-dimensional thermal model has been developed to study the effect of the presence of landmines in the thermal signature of the bare soil. Based on this model, a target identification procedure is proposed aiming at detecting and classifying the anomalies found on the soil thermal signature. In our approach, landmines are thought of as a thermal barrier in the natural flow of the heat inside the soil, which produces a perturbation of the expected thermal pattern on the surface. The detection of these perturbations will put into evidence the presence of potential mine targets. We propose an iterative procedure to classify the detected perturbations as mines or nonmines and to estimate their depth of burial. This paper describes the main principles of our method and illustrates classification results on a set of acquired images. Qualitative and quantitative comparisons with independent component analysis are also given.

Genetic algorithms are applied to design multilayer discrete-time cellular neural networks for image processing tasks, To this end not only the templates of the different layers will be optimized, but also the network structure itself, that is, number of layers and iterations per layer. As a difference with traditional strategies, both the definition of the optimum network size and the template optimization are done simultaneously.

Detection and clearance of buried mines is a big problem with lots of humanitarian, environmental and economic implications. Classic techniques, such as metal detectors, are not suitable for detecting mines with low or null metal content. In this work we propose a novel method based on the analysis of the different thermodynamic behaviour of the mines and the soil using a sequence of infrared images. In order to process this information, we propose the use of a specific type of neural network characterized by its parallel nature, high processing speed, low cost and power consumption and small size.