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Gerd Krüger 0001

dblp:17/4371-1 · DBLP profile ↗
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3ranked-venue papers
3as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 93% Processor architecture and microarchitecture · 7%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › design for testability
built-in self-test
0.021991
A tool for hierarchical test generation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Automatic generation of self-test programs - a new feature of the MIMOLA design system · DAC 1986
Electronic design automation
hardware verification and test
0.021991
A tool for hierarchical test generation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Automatic generation of self-test programs - a new feature of the MIMOLA design system · DAC 1986
Electronic design automation › hardware verification and test
design for testability
0.011991
A tool for hierarchical test generation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Electronic design automation › hardware verification and test › test generation › high-level test generation
hierarchical test generation
0.011991
A tool for hierarchical test generation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Electronic design automation › hardware verification and test
test generation
0.011991
A tool for hierarchical test generation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Processor architecture and microarchitecture
microprocessor
0.011991
A tool for hierarchical test generation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Processor architecture and microarchitecture › microprogramming
microprogrammable processor
0.011986
Automatic generation of self-test programs - a new feature of the MIMOLA design system · DAC 1986

Methods — techniques the papers use, named apart from their topics

mixed-level test generation · 0.0automatic test program generation · 0.0
YearPublicationVenuePosition
1991 A tool for hierarchical test generation
abstract
An extended system MSST (MIMOLA software system test generator), and its algorithms for automatic test generation are presented. In a hierarchical, mixed-level approach (from gate to system level) test patterns for sequential circuits and test programs for external testing or self-testing (diagnostics) of microprocessor boards or processor systems can be generated automatically. In a complete hierarchy lower bounds for test coverage are easily computable. The MIMOLA design system (including MSST) has been installed on VAX, APOLLO, SUN, and several other host machines. Several production line test applications show good results.>
Gerd Krüger 0001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
1988 A tool for hierarchical test generation
abstract
An extended system for automatic test generation and its algorithm are presented. In a hierarchical mixed-level approach (from gate- to system-level), test patterns for sequential circuits of arbitrary depth, and even test programs for either external or self-test of microprocessor boards or processor systems, can be generated automatically. In a complete hierarchy, lower bounds for test coverage are easily computable. Applications in real production-line testing have shown good results.>
Gerd Krüger 0001
ICCAD1
1986 Automatic generation of self-test programs - a new feature of the MIMOLA design system
abstract
A method to automatically generate functional self-test programs for arbitrary processor systems including microprogrammable and custom designed special purpose types is presented. Only commonly available user information is needed, but gate-level details can be utilized as well. The generated self-test programs perform user guided tests for memory function and register decoding, functional or gate-level derived tests for combinational modules, and a machine status check to detect undesired side-effects. The programs are given in the micro- or machine code of the target system, ready for execution. First applications have shown promising results.
Gerd Krüger 0001
DAC1