In this paper, we propose AMS-IO-Agent, a domain-specialized LLM-based agent for structure-aware input/output (I/O) subsystem generation in analog and mixed-signal (AMS) integrated circuits (ICs). The central contribution of this work is a framework that connects natural language design intent with industrial-level AMS IC design deliverables. AMS-IO-Agent integrates two key capabilities: (1) a structured domain knowledge base that captures reusable constraints and design conventions; (2) design intent structuring, which converts ambiguous user intent into verifiable logic steps using JSON and Python as intermediate formats. We further introduce AMS-IO-Bench, a benchmark for wirebond-packaged AMS I/O ring automation. On this benchmark, AMS-IO-Agent achieves over 70% DRC+LVS pass rate and reduces design turnaround time from hours to minutes, outperforming the baseline LLM. Furthermore, an agent-generated I/O ring was fabricated and validated in a 28 nm CMOS tape-out, demonstrating the practical effectiveness of the approach in real AMS IC design flows. To our knowledge, this is the first reported human-agent collaborative AMS IC design in which an LLM-based agent completes a nontrivial subtask with outputs directly used in silicon.

This article presents a method for the analysis of power supply rejection (PSR) of low-dropout regulators (LDOs), especially for those with a buffer stage. To determine the optimal design combination for each block in an LDO, we analyze and categorize ripple-coupling paths in LDOs with a buffer stage using a small-signal model based on the open-loop PSR concept. High frequency characteristics of the LDO power stage with and without an off-chip load capacitor are also analyzed in detail to extend the proposed method to very high frequencies, and to optimize the PSR performance at high frequencies. And then the co-design of open-loop PSR and feedback loop dynamics is analyzed to facilitate an informed design procedure for optimized overall PSR. Finally, we implement an output-capacitorless LDO with a buffer stage to verify the analyses in this work. In this design example, the effects of the reduced rdsof the power transistor in an advanced process with very low dropout voltage are discussed and a feed forward ripple cancellation (FFRC) scheme is implemented to further enhance the PSR performance.

This paper presents a two-channel time-interleaved (TI) noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with wide bandwidth, high resolution, and low power consumption. A shared loop filter realizes residue filtering between interleaved channels by midway feedback. The error feedback-cascaded integrator feedforward (EF-CIFF) loop filter architecture is adopted to achieve 3rd-order noise shaping with only one residue amplifier. A ring buffer is adopted to provide accurate gain by forming an inner feedback loop. PVT robust biasing and split current source architecture make the ring buffer immune to PVT variation and VCMmismatch. A prototype ADC in 28nm CMOS achieves 62.0 dB SNDR over 75 MHz bandwidth and consumes 5.9 mW, leading to a FoMs of 163 dB.

This paper introduces a hierarchical compilation approach for multi-channel reconfigurable analog-to-digital converter (ADC) systems, motivated by the need for highly flexible and scalable solutions in programmable converter arrays (PCAs). Unlike existing methods that mainly rely on manual circuitlevel adjustments with high complexity, limited scalability, and low flexibility, this method provides a structured and scalable hierarchical mapping scheme. This facilitates flexible and efficient configuration by integrating software and hardware design, making it highly suitable for automation and future expansion. It paves the way for the automatic synthesis, optimization and future expansion of PCAs.

This live demonstration presents a highly programmable analog-to-digital converter (ADC). The ADC is composed of an array of conversion blocks, each of which can be individually programmed. These conversion blocks can collaborate through a flexible bus system to achieve a wide range of functionalities and performance coverage. An interactive online programming system based on Matlab intuitively demonstrates how the ADC chip can be easily programmed. Additionally, the system includes a design rule check function to ensure programming validity, and a simulator to predict the actual performance. The system showcases an ADC performance range of MHz to GHz bandwidth and 30dB to 80dB SNDR.

Accurate cell type classification is critical for downstream analysis in single-cell RNA sequencing (scRNA-seq). Most existing methods rely on a single type of feature representation-such as statistical, information theory, matrix factorization, or deep learning-based features. However, each captures different aspects of the data, and no single feature type can fully represent the complex differences between cell types. Moreover, naïvely concatenating multiple features may introduce redundancy or noise, reducing model performance. To address these challenges, we propose scMFF, which is a multiple feature fusion framework that integrates four features and explores six fusion strategies in combination with various classifiers for single-cell type classification. Comprehensive evaluations on 42 disease-related datasets and an external COVID-19 dataset demonstrate that scMFF outperforms single-feature approaches in terms of performance and stability, providing a reliable and effective solution for scRNA-seq data analysis.

This paper presents a 7.68MSps 20kHz-BW nested continuous-time (CT) delta-sigma modulator (DSM) analog-to-digital converter (ADC). The nested DSM is composed of an inner analog CT DSM and a weighted multi-threshold MSB-pass quantization path. In the inner analog CT DSM, a negative-R-based cross-RC integrator structure is employed to reduce the resistance by 8×, thus improving area efficiency and alleviating parasitic issues introduced by large standard poly resistors. In the MSB-pass quantization path, several techniques including weighted counting, multi-threshold MSB-pass comparison, look-ahead comparison, and consecutive identical state detection are proposed. These techniques help to double the speed of the proposed nested DSM over the conventional nested DSM. Fabricated in a 180nm CMOS, the prototype DSM achieves SNR/SNDR/SFDR of 108.3dB/107.3dB/121.6dBc, with maximum resistance of only 179kΩ in the loop filter. The measured Schreier figure of merit (FoMS) is 183.6dB.

This work presents a new analog-to-digital converter (ADC) architecture named programmable converter array (PCA) for multi-standard signal acquisition. Unlike prior reconfigurable ADCs that are mainly configured at the circuit level, PCA is highly flexible at the architecture level and can process multiple input signals simultaneously for mode concurrency. The elemental units in the converter array are Conversion Blocks (CBs) based on successive approximation register (SAR) ADCs. Multiple CBs can interleave or run synergically through a bus system to form sophisticated architectures. Fabricated in 28nm CMOS, the prototype converter array can be configured as over 16 modes, with an SNDR range from 30dB to 82dB and an aggregate bandwidth from sub-MHz to 1000MHz. The prototype achieves a peak Schreier figure of merit (FoMs) of 176dB while maintaining FoMs over 165dB in most configurations, and occupies only 0.1mm2 of silicon area.

This work proposes a dithered-digital-mixing background timing-skew calibration method for time-interleaved (TI) analog-to-digital converters (ADCs). Unlike prior digital-mixing methods that limit the input bandwidth or lead the calibration process to a limit cycle, the proposed method enhances the input bandwidth to the Nyquist frequency and guarantees the convergence. This is achieved by a pseudo-random binary sequence generator that produces a dither signal. Practical considerations including thermal noise and the step size of variable delay lines are discussed. Behavioral simulation results demonstrate the effectiveness of the proposed method with an improvement of signal-to-noise-and-distortion ratio from 26.3dB to 52.6dB for a 5GS/s 9b 16-channel TI ADC.

With the rapid advances of deep learning-based computer vision (CV) technology, digital images are increasingly consumed, not by humans, but by downstream CV algorithms. However, capturing high-fidelity and high-resolution images is energy-intensive. It not only dominates the energy consumption of the sensor itself (i.e. in low-power edge devices), but also contributes to significant memory burdens and performance bottlenecks in the later storage, processing, and communication stages. In this paper, we systematically explore a new paradigm of in-sensor processing, termed "learned compressive acquisition" (LeCA). Targeting machine vision applications on the edge, the LeCA framework exploits the joint learning of a sensor autoencoder structure with the downstream CV algorithms to effectively compress the original image into low-dimensional features with adaptive bit depth. We employ column-parallel analog-domain processing directly inside the image sensor to perform the compressive encoding of the raw image, resulting in meaningful hardware savings, and energy efficiency improvements. Evaluated within a modern machine vision processing pipeline, LeCA achieves 4×, 6×, and 8× compression ratios prior to any digital compression, with minimal accuracy loss of 0.97%, 0.98%, and 2.01% on ImageNet, outperforming existing methods. Compared with the conventional full-resolution image sensor and the state-of-the-art compressive sensing sensor, our LeCA sensor is 6.3× and 2.2× more energy-efficient while reaching a 2× higher compression ratio.

This paper presents a 13-tap FIR filter and an IIR filter embedded in a 10-bit SAR ADC for wireless communications chip. The IIR filter can be inherently realized through reusing the capacitor array of the SAR ADC, thus improving the stopband suppression and shaping the transition band. Besides, the DC attenuation is also avoided. The sampling rate loss of the SAR ADC can be compensated by the$4\times $time-interleaving technology. The proposed filter features high power-efficient, linearity and process compatibility. Compared with a 15-tap FIR filter, the out-of-band suppression at the cut-off frequency (OOBS@$f_{\mathrm {cut-off}}$) is enhanced by 9dB theoretically. A prototype FIR/IIR filter in 40nm CMOS occupies an active area of 0.067mm2, consumes$38~\mu \text{W}$at a single supply of 1.1V, has a 1-MHz bandwidth, obtains$>$42.2dB [email protected] when operated at 40MS/s. Meanwhile, the SAR ADC without/with the proposed filter can achieve a FoMw of 7.91 fJ/conversion-step and 13.5 fJ/conversion-step, respectively.

This paper presents an approach to the mitigation of harmonic distortions in wideband current-steering digital-to-analog converters (DACs). This approach enables code-independent constant-switching-activity data-weighted-averaging (CSA-DWA) with the extra area and power overhead by exploiting redundant current sources. With CSA-DWA, a 16-bit 4.0-GS/s calibration-free DAC is designed in 65 nm CMOS. To achieve high-speed low-complexity CSA-DWA decoding, the most-significant-bit (MSB) segment is set to 5 bits. The MSB switching activities are regulated to be constant with 1-bit randomized switching activity to minimize the non-linearity due to the MSB switching activity truncation errors in the CSA-DWA decoder. Furthermore, a power delivery scheme is adopted to reduce the IR-drop mismatch between the switching elements. Experimental results show that this DAC achieves$>$70 dBc spurious-free dynamic range (SFDR) and$< -80$dBc third-order intermodulation distortion (IM3) up to 1 GHz. With the proposed CSA-DWA, SFDR and IM3 are improved by 4–15 dB and 5–14 dB, respectively, across the Nyquist band.

Generating wells for transistors is an essential challenge in analog circuit layout synthesis. While it is closely related to analog placement, very little research has explicitly considered well generation within the placement process. In this work, we propose a new analytical well-aware analog placer. It uses a generative adversarial network (GAN) for generating wells and guides the placement process. A global placement algorithm spreads the modules given the GAN guidance and optimizes for area and wirelength. Well-aware legalization techniques then legalize the global placement results and produce the final placement solutions. By allowing well sharing between transistors and explicitly considering wells in placement, the proposed framework achieves more than 74% improvement in the area and more than 26% reduction in half-perimeter wirelength over existing placement methodologies in experimental results.

High-speed time-interleaved analog-to-digital converters (TI-ADCs) are sensitive to timing skew mismatch. Autocorrelation-based background timing skew calibration techniques require small hardware overhead as they rely on the TI-ADC input signal for calibration. However, such techniques suffer from a very long convergence time. This paper proposes a new correlation-based technique that boosts convergence speed by orders of magnitude compared to existing autocorrelation-based techniques. The technique uses a digital window detector and calculates the signal correlation funnction around zero-crossings only. Practical design considerations including thermal noise, clock jitter, quantization and offset mismatch are discussed. Behavioral simulation results for two TI-ADCs with different speeds, resolutions and interleaving factors are presented.

This paper presents a second-order VCO-based $\Delta\Sigma$ ADC with a fully digital feedback adder, which is highly digital, area efficient and low power. Both the first and second loop integrator are implemented by VCOs and are free of OTA. A novel digital adder is proposed to realize the secondary feedback, significantly reducing the power and area of the second stage. The proposed ADC is designed in a 28nm CMOS technology under 0.9V supply, consuming only 1.14mW. The simulated SNDR and SFDR are 72.5dB and 84.1dB respectively over a 5MHz signal bandwidth.

Machine learning-assisted global optimization methods for speeding up analog integrated circuit sizing is attracting much attention. However, often a few typical analog integrated circuit design specifications are considered in most relevant research. When considering the complete set of specifications, two main challenges are yet to be addressed: 1) the prediction error for some performances may be large and the prediction error is accumulated by many performances. This may mislead the optimization and fail the sizing, especially when the specifications are stringent and 2) the machine learning cost could be high considering the number of specifications, considerably canceling out the time saved. A new method, called efficient surrogate model-assisted sizing method for high-performance analog building blocks (ESSAB), is proposed in this article to address the above challenges. The key innovations include a new candidate design ranking method and a new artificial neural network model construction method for analog circuit performance. Experiments using two amplifiers and a comparator with a complete set of stringent design specifications show the advantages of ESSAB.

This work presents an always-on reference ripple cancellation technique that actively cancels the reference settling error throughout the entire SAR conversion process. Unlike the conventional designs that require high-speed reference buffers or large on-chip decoupling capacitors to minimize the error, it incorporates an extra path to actively cancel the error, which can provide considerable reference ripple tolerance, thus significantly relaxing the reference settling requirement. To verify the proposed technique, a prototype 10-bit 100-MS/s SAR ADC is fabricated in a 40-nm CMOS process. Equipped with the proposed technique, it only requires a 0.5-pF decoupling capacitor and an on-chip low-power reference buffer consuming 0.26-mW static power. The proposed technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL) and differential non-linearity (DNL) by 15 times. Overall, the prototype ADC achieves an SNDR of 56.3 dB at Nyquist rate while consuming 1.4 mW,includingon-chip reference buffers.

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.

Analog circuit sizing takes a significant amount of manual effort in a typical design cycle. With rapidly developing technology and tight schedules, bringing automated solutions for sizing has attracted great attention. This paper presents DNN-Opt, a Reinforcement Learning (RL) inspired Deep Neural Network (DNN) based black-box optimization framework for analog circuit sizing. The key contributions of this paper are a novel sample-efficient two-stage deep learning optimization framework leveraging RL actor-critic algorithms, and a recipe to extend it on large industrial circuits using critical device identification. Our method shows 5—30x sample efficiency compared to other black-box optimization methods both on small building blocks and on large industrial circuits with better performance metrics. To the best of our knowledge, this is the first application of DNN-based circuit sizing on industrial scale circuits.

Recent research trends in analog layout synthesis aim for a fully automated netlist-to-GDSII design flow with minimum human efforts. Due to the sensitiveness of analog circuit layouts, symmetry matching between critical building blocks and devices can significantly impact the overall circuit performance. Therefore, providing accurate symmetry constraints for automated layout synthesis tools is crucial to achieving high-quality layouts. This paper presents a novel graph-learning-based framework leveraging unsupervised learning to recognize circuit matching structures by making the most of numerous unlabeled circuits. The proposed framework supports both system-level and device-level symmetry constraints extraction for various large-scale analog/mixed-signal systems. Experimental results show that our framework outperforms state-of-the-art symmetry constraint detection algorithms with remarkable accuracy and runtime improvement.

Despite recent developments in automated analog sizing and analog layout generation, there is doubt whether analog design automation techniques could scale to system-level designs. On the other hand, analog designs are considered major roadblocks for open source hardware with limited available design automation tools. In this work, we present OpenSAR, the first open source automated end-to-end successive approximation register (SAR) analog-to-digital converter (ADC) compiler. OpenSAR only requires system performance specifications as the minimal input and outputs DRC and LVS clean layouts. Compared with prior work, we leverage automated placement and routing to generate analog building blocks, removing the need to design layout templates or libraries. We optimize the redundant non-binary capacitor digital-to-analog converter (CDAC) array design for yield considerations with a template-based layout generator that interleaves capacitor rows and columns to reduce process gradient mismatch. Post layout simulations demonstrate that the generated prototype designs achieve state-of-the-art resolution, speed, and energy efficiency.

In this work, we report the portable NMR system which provides solutions to the existing problems in miniature CMOS NMR systems. First, a higher IF of 50 kHz is achieved by exploiting separate frequencies for sample excitation and LO, thereby having higher immunity to 1/f noise. The proposed phase detector circuit aligns the experiment trigger with the constant phase difference between two frequencies. It maintains the constant RX output phase in every experiment, allowing the direct signal averaging without extra phase correction. In addition, 40X faster RX recovery with RX BW switching enables the signal acquisition with the dead time of 10$\mu \text{s}$. Fast settling improves the acquisition sensitivity. Lastly, a frequency calibration method based on signal peak detection is proposed. Combining the techniques with the fully integrated NMR transceivers, the system demonstrates the NMR experiments to measure the decaying time constant of less than 100$\mu \text{s}$. Furthermore, NMR diffusion experiments are performed with the echo spacing of$0.2\sim 8$ms.

Since the power consumption of data centers keeps increasing, a 48-V rack power distribution system replaces the conventional 12-V power bus to reduce the power delivery IR losses. Meanwhile, the 48 V needs conversion into 1 V or lower at the point-of-load for microprocessors. A 48V-to-12V DC-DC converter can serve as a first stage between the huge gap of 48V-to-1V, in a two-stage voltage regulator module (VRM). Thus, this paper presents a 3-phase resonant switched-capacitor ( 3Φ-ReSC) converter as the first stage of the VRM. Different from the reported solutions, 3-phase resonant operation reduces the current stress across each small-size GaN switch, and thus improves the power conversion efficiency. In addition, we also present the theoretical analysis and design procedures for the 3Φ-ReSC converter. We demonstrated the proposed 3Φ-ReSC converter with a 98% peak power efficiency at an output current of about 1 A, with a maximum output current of 10 A.

Symmetry and matching between critical building blocks have a significant impact on analog system performance. However, there is limited research on generating system level symmetry constraints. In this paper, we propose a novel method of detecting system symmetry constraints for analog circuits with graph similarity. Leveraging spectral graph analysis and graph centrality, the proposed algorithm can be applied to circuits and systems of large scale and different architectures. To the best of our knowledge, this is the first work in detecting system level symmetry constraints for analog and mixed-signal (AMS) circuits. Experimental results show that the proposed method can achieve high accuracy of 88.3% with low false alarm rate of less than 1.1% in largescale AMS designs.

Automatic transistor sizing is a challenging problem in circuit design due to the large design space, complex performance tradeoffs, and fast technology advancements. Although there have been plenty of work on transistor sizing targeting on one circuit, limited research has been done on transferring the knowledge from one circuit to another to reduce the re-design overhead. In this paper, we present GCN-RL Circuit Designer, leveraging reinforcement learning (RL) to transfer the knowledge between different technology nodes and topologies. Moreover, inspired by the simple fact that circuit is a graph, we learn on the circuit topology representation with graph convolutional neural networks (GCN). The GCN-RL agent extracts features of the topology graph whose vertices are transistors, edges are wires. Our learning-based optimization consistently achieves the highest Figures of Merit (FoM) on four different circuits compared with conventional black box optimization methods (Bayesian Optimization, Evolutionary Algorithms), random search and human expert designs. Experiments on transfer learning between five technology nodes and two circuit topologies demonstrate that RL with transfer learning can achieve much higher FoMs than methods without knowledge transfer. Our transferable optimization method makes transistor sizing and design porting more effective and efficient.

Existing analog layout synthesis tools provide little guarantee to post layout performance and have limited capabilities of handling system-level designs. In this paper, we present a closed-loop hierarchical analog layout synthesizer, capable of handling system designs. To ensure system performance, the building block layout implementations are optimized efficiently, utilizing post layout simulations with multi-objective Bayesian optimization. To the best of our knowledge, this is the first work demonstrating success in automated layout synthesis on generic analog system designs. Experimental results show our synthesized continuous-time ΔΣ modulator (CTDSM) achieves post layout performance of 65.9dB in signal to noise and distortion ratio (SNDR), compared with 67.8dB in the schematic design.

Despite tremendous efforts in analog layout automation, little adoption has been demonstrated in practical design flows. Traditional analog layout synthesis tools use various heuristic constraints to prune the design space to ensure post layout performance. However, these approaches provide limited guarantee and poor generalizability due to a lack of model mapping layout properties to circuit performance. In this paper, we attempt to shorten the gap in post layout performance modeling for analog circuits with a quantitative statistical approach. We leverage a state-of-the-art automatic analog layout tool and industry-level simulator to generate labeled training data in an automated manner. We propose a 3D convolutional neural network (CNN) model to predict the relative placement quality using well-crafted placement features. To achieve data-efficiency for practical usage, we further propose a transfer learning scheme that greatly reduces the amount of data needed. Our model would enable early pruning and efficient design explorations for practical layout design flows. Experimental results demonstrate the effectiveness and generalizability of our method across different operational transconductance amplifier (OTA) designs.

Placement is among the most critical steps in analog/mixed-signal (AMS) circuit layout synthesis. It implicitly determines the wiring topology and therefore has considerable impacts on post-layout parasitics and coupling. Existing analog placement techniques are mainly focusing on geometric constraints in analog building blocks. However, there yet lacks an effective way to consider the systemlevel signal flow for sensitive AMS circuits. Leveraging prior knowledge from schematics, we propose to consider the critical signal paths in automatic AMS placement and present an efficient framework. Experimental results demonstrate our proposed framework's efficiency and effectiveness with a 22.8% reduction in routed wire-length compared to state-of-the-art AMS placer and 10 dB improvement in the signal-to-noise-and-distortion ratio (SNDR) for an ADC.

Detailed routing is an intricate and tedious procedure in design automation and has become a crucial step for advanced node enablement. Compared with its advances in digital design, detailed routing for analog/mixed-signal (AMS) integrated circuits (ICs) is still heavily manual. In AMS designs, the sensitive net coupling issues and analog-specific constraints make detailed routing even more challenging. This work presents a novel and efficient detailed routing framework for automated AMS layout synthesis considering industrial design rules as well as analog-specific geometric and electrical constraints. Experimental results demonstrate the efficiency and effectiveness of our approach in optimizing circuit performance while satisfying the specified constraints. Post-layout simulations further prove that our detailed routing results can achieve sign-off quality.

Flexible capacitive pressure sensing system (FCPSS) is promising in the area of healthcare, robotics, and Internet of Things (IoT). As the size of the sensing array increases, designing energy-efficient FCPSS is getting challenging. This work provides a comprehensive solution for low-power FCPSS design, where major contributions are as follows. 1) Crosstalk-induced measurement error in a crossbar structure FCPSS is first studied and an accurate and low-power linear iterative algorithm is proposed for on-chip sensing array calibration (SAC). 2) Binary Neural Network (BNN)-based spatial-temporal adaptive sensing scheme for FCPSS is first proposed to utilize the sparsity of sampling and to further improve energy efficiency. Combined with the clock-gating-friendly low-power sensor interface, the system consumes 31.39 μJ energy and gains 95.04% capacitor measurement accuracy for each sensing operation on a 10×10 array, achieving 116× energy reduction compared with the state-of-the-art technology.

In back-end analog/mixed-signal (AMS) design flow, well generation persists as a fundamental challenge for layout compactness, routing complexity, circuit performance and robustness. The immaturity of AMS layout automation tools comes to a large extent from the difficulty in comprehending and incorporating designer expertise. To mimic the behavior of experienced designers in well generation, we propose a generative adversarial network (GAN) guided well generation framework with a post-refinement stage leveraging the previous high-quality manually-crafted layouts. Guiding regions for wells are first created by a trained GAN model, after which the well generation results are legalized through post-refinement to satisfy design rules. Experimental results show that the proposed technique is able to generate wells close to manual designs with comparable post-layout circuit performance.

Despite tremendous advancement of digital IC design automation tools over the last few decades, analog IC layout is still heavily manual which is very tedious and error-prone. This paper will first review the history, challenges, and current status of analog IC layout automation. Then, we will present MAGICAL, a human-intelligence inspired, fully-automated analog IC layout system currently being developed under the DARPA IDEA program. It starts from an unannotated netlist, performs automatic layout constraint extraction and device generation, then performs placement and post-placement optimization, followed by routing to obtain the final GDSII layout. Various analytical, heuristic, and machine learning algorithms will be discussed. MAGICAL has obtained promising preliminary results. We will conclude the paper with further discussions on challenges and future directions for fully-automated analog IC layout.

Due to sensitive layout-dependent effects and varied performance metrics, analog routing automation for performance-driven layout synthesis is difficult to generalize. Existing research has proposed a number of heuristic layout constraints targeting specific performance metrics. However, previous frameworks fail to automatically combine routing with human intelligence. This paper proposes a novel, fully automated, analog routing paradigm that leverages machine learning to provide routing guidance, mimicking the sophisticated manual layout approaches. Experiments show that the proposed methodology obtains significant improvements over existing techniques and achieves competitive performance to manual layouts while being capable of generalizing to circuits of different functionality.

The layouts of analog/mixed-signal (AMS) integrated circuits (ICs) are dramatically different from their digital counterparts. AMS circuit layouts usually include a variety of devices, including transistors, capacitors, resistors, and inductors. A complicated AMS IC system with hierarchical structure may also consist of pre-laid out subcircuits. Different types of devices can occupy different manufacturing layers. Therefore, during the layout stage, the devices require co-optimization to achieve high circuit performance. Leveraging the fact that some devices can be built by mutually exclusive layers, they can be carefully designed to overlap each other to effectively reduce the total area and wirelength without degrading the circuit performance. In this paper, we propose an analytical framework to tackle the device layer-aware analog placement problem. Experimental results show that on average the proposed techniques can reduce the total area and half-perimeter wirelength by 9% and 23%, respectively. To verify the routability of the placement results, we also develop an analog global router, which demonstrates that the device layer-aware placement can achieve 18% shorter wirelength during global routing.

Ring oscillators (ROs) are increasingly being used for ΔΣ ADC. This is because of the highly digital nature of ROs which makes them very amenable for design in scaled CMOS technologies. This work presents recent advances in RO based ΔΣ ADCs. In addition to being low power and scaling friendly, ring oscillators also possess intrinsic integration and quantization properties, which make them well suited for oversampling ADC applications. This work presents a review on both discrete-time and continuous-time ring oscillator based delta-sigma ADCs, as well as a novel second-order phase-locked loop (PLL)-like ring oscillator based ΔΣ ADC.

Conventional analog/mixed-signal (AMS) circuits design methodology relying heavily on the use of operational amplifiers (opamps) to process signals in voltage-domain (VD) encounters severe difficulties in advanced nanometer-scale CMOS process. We present a novel scaling compatible, synthesis friendly ring voltage-controlled oscillator (VCO) based time-domain (TD) delta-sigma analog-to-digital converter (ADC) whose performance improves as technology advances. Decomposed into digital gates (e.g. inverters) and a small set of simple customized cells (e.g. resistors), its layout is fully synthesizable by leveraging digital layout synthesis tools. Post-layout simulation results demonstrate the scaling compatibility of the proposed ADC and a drastic boost to design productivity.

High-performance analog integrated circuits usually require minimizing critical parasitic loading, which can be modeled by the critical net wire length in the layout stage. In order to reduce post-layout circuit performance degradation, critical net wire length minimization should be considered during placement, in addition to the conventional optimization objectives of total area and half perimeter wire length (HPWL). In this paper, we develop effective hierarchical and analytical techniques for high-performance analog circuits placement, which is a complex problem given its multi-objectives and constraints (e.g. hierarchical symmetric groups). The entire circuit is first partitioned hierarchically in a top-down, critical parasitics aware, hierarchical symmetric constraints and proximity constraints feasible manner, where the placement subproblem for each partition at each level can be solved in reasonable run-time. Then, different placement variants are generated for each partition from bottom up, taking advantage of the computation power of modern multi-core systems with parallelization. To assemble the placement variants of different subpartitions, a Mixed Integer Linear Programming (MILP) formulation is proposed which can simultaneously minimize critical parasitic loading, total area and HPWL, and handle hierarchical symmetric constraints, module variants selection and orientation. Experimental results demonstrate the effectiveness of the proposed techniques.

Real-world computationally expensive design optimization problems with discrete variables pose challenges to surrogate-based optimization methods in terms of both efficiency and search ability. In this paper, a new method is introduced, called surrogate model-aware differential evolution with neighbourhood exploration, which has two phases. The first phase adopts a surrogate-based optimization method based on efficient surrogate model-aware search framework, the goal of which is to reach at least the neighbourhood of the global optimum. In the second phase, a neighbourhood exploration method for discrete variables is developed and collaborates with the first phase to further improve the obtained solutions. Empirical studies on various benchmark problems and a real-world network-on-chip design optimization problem show the combined advantages in terms of efficiency and search ability: when only a very limited number of exact evaluations are allowed, the proposed method is not slower than one of the most efficient methods for the targeted problem; when more evaluations are allowed, the proposed method can obtain results with comparable quality compared to standard differential evolution, but it requires only 1% to 30% of exact function evaluations.

The effects of comparator input common-mode voltage Vcmare analyzed in this paper. The analysis clearly shows a trade-off in the choice of Vcmin terms of offset, noise, power and speed. Based on the analysis, an energy efficient SAR ADC switching technique is proposed with less Vcmvariation and better linearity compared with the widely used monotonic switching technique. Both the simulation results and prototype measured results match with the analysis.

A novel digital calibration technique is proposed to calibrate the capacitor mismatch in SAR ADCs. The capacitor mismatches are extracted based on the comparator metastability and intrinsic noise. The proposed technique does not require additional external control sequences or any modification of the main DAC. The simulation results of a 12-bit SAR ADC with 10% capacitor mismatch show that the SNDR and SFDR are improved by 13.9dB and 34.9dB respectively with the proposed calibration technique. The calibration technique is effective under process variation based on a Monte-Carlo simulation.

This paper presents a calibration technique for radix-3 successive approximation register (SAR) analog-to-digital converter (ADC) that was proposed in [1]. The main advantage of radix-3 SAR ADC is it generates 1.6 bits per conversion cycle which is 60% faster than the conventional radix-2 SAR. However the performance largely depends on matching of capacitors in digital to analog converter (DAC). Effect of capacitor mismatches on signal-to-quantization-noise ratio (SQNR) is demonstrated and calibration technique is simulated in 180nm CMOS technology. This calibration technique does not require any extra capacitor DAC and is programmable for any radix-3 SAR ADC. 7 bit Radix-3 ADC is designed which can achieve signal to noise and distortion ratio (SNDR) of 67 dB up to 10% capacitor mismatch.

This paper shows frequency dependence of switching energy of bottom-plate sampled successive approximation register (SAR) analog-to-digital converters (ADC) and presents a technique that achieves 86% reduction in switching energy compared to the conventional SAR over a wide frequency range. The switching energy has been calculated by taking into account both the power drawn from reference as well as the power consumed by the switches themselves. The results have been verified through MATLAB and SPICE simulations.

This paper presents an improved ISI shaping technique for multi-bit ΔΣ DACs. Compared to the prior ISI shaping method (Lars Risbo et al, JSSC, 2011) that monitors only the up (0 → 1) transitions, the proposed technique makes use of both the up and down (1 → 0) transitions with negligible hardware cost. It provides a finer control of the transition activity, thereby improving the ISI shaping effect. In addition, due to the tight coupling between the ISI and mismatch shaping loops, the proposed technique also improves the mismatch shaping result. Simulation results show that it can reduce ISI induced distortions by 10 dB compared to the prior ISI shaping technique and 50 dB compared to DWA.

This paper presents a simple but high performance architecture for multi-channel analog-to-digital conversion. Based on compressive sensing, only one SAR ADC is needed to convert multi-channel sparse inputs, leading to significant analog power saving and hardware saving. Moreover, it helps avoid problems occurring in conventional multi-channel ADCs such as timing skew, offset mismatch, and gain mismatch. A 12-bit SAR ADC converting 4-channel sparse signals simultaneously is designed in 130nm CMOS process. The design reaches a SNDR of 66.3dB and consumes an average power of 58μW at the sampling frequency of 1MHz. The L1minimization method is chosen to reconstruct the input signals. The single-tone and multi-tone inputs can be reconstructed with a minimum precision of 68dB and 55dB THD, respectively.

This paper presents an in-depth analysis of the generation of tones in the output spectra of vector-quantizer (VQ) based multibit mismatch-shaped ΔΣ digital-to-analog converters (DACs). Building upon the analysis, a simple yet elegant method of adding dither to remove tones from the output spectra is presented. It achieves a better mismatch shaping performance with a low hardware cost compared to existing dithering techniques.