Demo Data from EDBT 2026 / reviewers in the wild / expert
Alaaeldin A. Amin
dblp:17/5103
· DBLP profile ↗
3ranked-venue papers
2as first author
0since 2021 · last 2007
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-authorSecurity and privacy · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › hardware verification and test › design for testability
built-in self-test |
0.0 | 1 | 1997 | New fault models and efficient BIST algorithms for dual-port memories · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 1997 | New fault models and efficient BIST algorithms for dual-port memories · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997 |
Electronic design automation › hardware verification and test › design for testability › built-in self-test
memory BIST |
0.0 | 1 | 1997 | New fault models and efficient BIST algorithms for dual-port memories · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997 |
Electronic design automation › hardware verification and test
memory testing |
0.0 | 1 | 1997 | New fault models and efficient BIST algorithms for dual-port memories · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1997 |
Methods — techniques the papers use, named apart from their topics
test algorithm design · 0.0fault modeling · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2007 | Utilizing Extension Character 'Kashida' with Pointed Letters for Arabic Text Digital Watermarking
Adnan Abdul-Aziz Gutub, Lahouari Ghouti, Alaaeldin A. Amin, Talal M. Alkharobi, Mohammad K. Ibrahim |
SECRYPT | 3 |
| 1997 | New fault models and efficient BIST algorithms for dual-port memoriesabstractThe testability problem of dual-port memories is investigated. A functional model is defined, and architectural modifications to enhance the testability of such chips are described. These modifications allow multiple access of memory cells for increased test speed with minimal overhead on both silicon area and device performance. New fault models are proposed, and efficient O(/spl radic/n) test algorithms are described for both the memory array and the address decoders. The new fault models account for the simultaneous dual-access property of the device. In addition to the classical static neighborhood pattern-sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, duplex dynamic neighborhood pattern-sensitive faults (DDNPSF). Alaaeldin A. Amin, Mohamed Y. Osman, Radwan E. Abdel-Aal, Husni Al-Muhtaseb |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 1994 | Efficient O(sqrt(n)) BIST Algorithms for DDNPS Faults in Dual-Port MemoriesabstractThe testability problem of dual port memories is investigated. Architectural modifications which enhance testability with minimal overhead on both silicon area and device performance are described. New fault models for both the memory array and the address decoders are proposed and efficient O(/spl radic/n) test algorithms are presented. The new fault models account for the simultaneous dual access property of the device. In addition to the classical static neighborhood pattern sensitive faults, the array test algorithm covers a new class of pattern sensitive faults, Duplex Dynamic Neighborhood Pattern Sensitive faults (DDNPSF). Alaaeldin A. Amin, Mohamed Y. Osman, Radwan E. Abdel-Aal, Husni Al-Muhtaseb |
ITC | 1 |