Millimeter-wave (mmWave) systems require a large number of antennas, which makes the beam training challenging and time-consuming for conventional phased arrays. Recently, a true-time-delay (TTD) array-based beam training algorithm has been shown as an effective solution to overcome the training overhead in large arrays. In this paper, we present a custom-built over-the-air (OTA) testbed to study the effects of hardware impairments on the TTD-based beam training and verify its feasibility in a real system. We proposed an orthogonal matching pursuit (OMP) based reconstruction algorithm along with a phase calibration dictionary to combat nonidealities such as strong frequency selectivity and phase misalignment in the received raw IQ signal. Post-processing results showed that with the nonideality effects properly handled, the 3D TTD beam training algorithm can achieve high AOA estimation accuracy.

This paper presents a 14 GHz sub-sampling PLL (SSPLL) with its phase noise analysis for Ku-band wireless transceivers. The performance enhancement of the phase-locked loop (PLL) over single-stage PLL in terms of jitter and power consumption is theoretically presented and verified with measured results. The proposed capacitor multiplier reduces the size of the loop filter capacitor by 28 times. The active capacitor VCO decreases the out-band phase noise while consuming less power. Fabricated in a 65 nm CMOS process with a core active area of$0.0918~mm^{2}$, the SSPLL operates at 1.2 V supply achieving 13.2-14.8 GHz tuning range, 85.4 fs integrated jitter at 14 GHz, 8.42 mW power consumption, and −252.12 dB figure-of-merit (FoM). The measured results in-band and out-band phase noises of −108.6 dBc/Hz at a 1 MHz offset and −128.9 dBc/Hz at a 10 MHz offset, respectively.

Machine learning (ML) models have gained prominence in solving real-world tasks. However, implementing ML models is both compute- and memory-intensive. Domain-specific architectures such as Resistive Random Access Memory (ReRAM)-based Processing-in-Memory (PIM) platforms have been proposed to efficiently accelerate ML training and inference. However, existing ML workloads require a high amount of area and power for training. A major contributor to the area and power overheads is the Analog-to-Digital Converter (ADC). In this work, we propose a mixed pruning technique along with a novel reconfigurable ADC design to improve the power consumption profile. Overall, the pruned model with the reconfigurable ADC achieves ~50% reduction in power for training compared to existing state-of-the-art ReRAM-based architectures.

With the increasing complexity of highly integrated system on chips (SoCs), the power management system (PMS) is required to provide several power supplies efficiently for individual blocks. This paper presents a single-inductor multiple-output (SIMO) inductor-first hybrid converter that generates three outputs between 0.4V and 1.6V from a 1.8V input. The proposed multiple-output hybrid power stage can improve the conversion efficiency by reducing inductor current while extending the output voltage range compared with the existing hybrid topologies. In addition, the proposed converter employs an on-chip switched-capacitor power stage (SCPS) with a dual-switching frequency technique, resulting in a fast response time, low cross-regulation, and reduced number of on-chip pads. Measurement results show that the converter achieves a peak efficiency of 87.5% with the maximum output current of 450mA. The converter is integrated with a fast voltage regulation loop with 500MHz system clock to achieve a less than 0.01mA/mV cross-regulation and a maximum 20mV overshoot at full-load transient response. The design is fabricated in the standard 180nm CMOS technology.

A new boosted active-capacitor (BAC) architecture using LC-tuned active-impedance-conversion is presented. In the chosen frequency range, the proposed BAC acts as a tunable capacitance multiplier and negative-transconductance, but where the positive-transconductance is not multiplied. The BAC is used as a low-loss tunable capacitor bank element for designing a wide tuning range voltage-controlled oscillator (VCO). A current-reuse technique is used to lower power consumption and suppress potential parasitic oscillation modes. A zero-capacitance-variation biasing is proposed for a BAC-VCO robust against process, voltage, and temperature variations. The BAC designed in a 65 nm bulk CMOS process achieves a capacitance tuning ratio of 7.8 with a quality factor of higher than 20 across VCO's tuning range. The BAC-VCO prototype has a tuning range of 8.3-14.3 GHz using less than 5 mW core power and achieves FoMT of up to -202.4 dBc/Hz.

The best beam steering directions are estimated through beam training, which is one of the most important and challenging tasks in millimeter-wave and sub-terahertz communications. Novel array architectures and signal processing techniques are required to avoid prohibitive beam training overhead associated with large antenna arrays and narrow beams. In this work, we leverage recent developments in true-time-delay (TTD) arrays with large delay-bandwidth products to accelerate beam training using frequency-dependent probing beams. We propose and study two TTD architecture candidates, including analog and hybrid analog-digital arrays, that can facilitate beam training with only one wideband pilot. We also propose a suitable algorithm that requires a single pilot to achieve high-accuracy estimation of angle of arrival. The proposed array architectures are compared in terms of beam training requirements and performance, robustness to practical hardware impairments, and power consumption. The findings suggest that the analog and hybrid TTD arrays achieve a sub-degree beam alignment precision with 66% and 25% lower power consumption than a fully digital array, respectively. Our results yield important design trade-offs among the basic system parameters, power consumption, and accuracy of angle of arrival estimation in fast TTD beam training.

Efficiency of power management system (PMS) is one of the key performance metrics for highly integrated system on chips (SoCs). Towards the goal of improving power efficiency of SoCs, we make two key technical contributions in this paper. First, we develop a multi-output switched-capacitor voltage regulator (SCVR) with a new flying capacitor crossing technique (FCCT) and cloud-capacitor method. Second, to optimize the design parameters of SCVR, we introduce a novel machine¬learning (ML)-inspired optimization framework to reduce the number of expensive design simulations. Simulation shows that power loss of the multi-output SCVR with FCCT is reduced by more than 40% compared to conventional multiple single-output SCVRs. Our ML-based design optimization framework is able to achieve more than 90% reduction in the number of simulations needed to uncover optimized circuit parameters of the proposed SCVR.

3D Network-on-Chip (3D NoC) enables design of high-performance and energy-efficient manycore computing platforms. Two of the commonly used vertical interconnection technologies are: through silicon via (TSV) and near-field inductive coupling (NFIC). Both TSV- and NFIC-based links introduce additional area overhead. One of the possible ways to reduce the area overhead is to design partially connected 3D NoC with minimal effect on overall performance. The achievable performance of the partially connected 3D NoCs depends on the area, energy, and bandwidth of the vertical links. Moreover, the electromigration-induced failure of TSV is more severe than the misalignment-induced error in NFIC. By considering all these pertinent factors, we demonstrate that it is indeed possible to design a partially connected NFIC-based 3D NoC that performs as good as a fully connected TSV-based counterpart when the data rate is below a certain limit. For higher data rates, the partially connected TSV-based 3D NoC is a viable solution. However, NFIC-based 3D NoC is always more robust than the TSV-based counterpart.

I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades[1](seeFig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown inFig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade[2],[3]. At the same time, the energy per task has been decreasing at 10–100 X/decade, as shown inFig. 2, for several systems and system-on-chip subsystems[4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit[5].

This paper presents a dual-output switchedcapacitor voltage regulator (DOSCVR) with a new flying capacitor crossing technique (FCCT) to improve power efficiency. With the FCCT, the power loss of the DOSCVR is reduced by 28%, increasing the power efficiency by 7% compared with the power efficiency of the conventional method that generates two voltages using independent single-output SCVRs. This enhanced efficiency results in no area penalty since the total flying capacitance remains unchanged. A prototype is then implemented in a 0.13-μm CMOS process to validate the proposed scheme. The prototype simultaneously produces two regulated voltages of 0.44 and 0.88 V from an input voltage of 1.5 V. The output voltages are regulated by low-bound regulation with frequency modulation. The maximum output current is 12 mA with a total flying capacitance of 0.98 nF, and the measured peak efficiency is 78%.

A new reference-spur cancelation technique is presented for supply-regulated ring-oscillator-based integer-N phaselocked loops (PLLs). A passive RC filter is used to implement a feed-forward (FF) spur-coupling path to perform spur cancelation at the PLL control signal. The proposed technique achieves a simulated spur cancelation of about 22 dB at the first spur harmonic. The simulated postcancelation spur value is -79 dBc for an oscillator gain of 0.1 GHz/V and -46 dBc for an oscillator gain of 6 GHz/V. Spur cancelation is also robust against large process, voltage, and temperature variations in the gain and bandwidth of the FF path. A 1-GHz integerN PLL prototype in a 65-nm CMOS process has a measured cancelation of 19.5 and 13 dB at the first and the second spur harmonic, respectively, with 320 μW of total power consumption. The PLL prototype has an oscillator gain of 1.5 GHz/V, which results in a postcancelation spur of -53 dBc. The proposed zero-power technique is suitable for low-power PLLs as it achieves a large spur cancelation without requiring any additional power consumption or calibration.

Wireless interconnects using near-field inductive coupling (NFIC) enables contactless vertical communications necessary for the design of energy efficient and robust 3-D manycore systems. However, the achievable performance, energy efficiency, bandwidth, and associated area overhead of NFICs are intertwined imposing significant design challenges and tradeoffs to explore the optimum link configuration. To address these challenges, in this paper, we propose a holistic design approach for exploring energy-efficient NFICs and target to exploit the benefits of the NFICs in the context of efficient and reliable network-on-chip (NoC) design. The proposed design framework employs statistical link analysis to select optimum NFIC-link configuration and is significantly more efficient in terms of energy efficiency and area overhead compared to the state-of-the-art counterparts. We demonstrate that 3-D NoCs incorporating NFIC-enabled links outperform through-silicon-via (TSV) counterparts. In addition, the overall reliability of TSV- and NFIC-enabled hybrid 3-D NoC is significantly better than only TSV-based NoCs in order to counteract the electromigration and workload-induced stress challenges.

3D integration, a breakthrough technology to achieve "More Moore and More Than Moore," provides numerous benefits such as better performance, lower power consumption, and wide bandwidth by vertical interconnects and 3D stacking. These vertical interconnects enable design of high performance 3D Network-on-Chip (NoC) as a communication backbone for massive manycore platforms. However, existing 3D NoCs are still bottlenecked due to simple extension of 2D architectures without fully exploiting the advantages of the 3D integration. Moreover, the anticipated performance gain of 3D NoC-enabled manycore chips will be compromised due to potential failures of through silicon vias (TSVs) that are predominantly used as vertical interconnects. To address these problems, we explore a holistic design methodology starting from the physical layer to the overall interconnection architecture where the vertical data exchange takes place through contactless links using near field inductive coupling (NFIC).

Near Field Inductive Coupling (NFIC) enables design of energy efficient and robust three-dimensional (3D) manycore systems. The associated design challenges and the trade-offs of the NFIC-based vertical links depend on achievable data-rates, energy and area overheads. In this work, we propose a holistic design flow that explores optimum energy and area efficient NFIC-link design as a communication backbone in a 3D manycore chip. Moreover, the design framework employs statistical link analysis to select optimum NFIC link configuration. The proposed NFIC-link design is significantly more efficient in terms of energy efficiency and area overhead compared to state-of-the-art counterpart. Energy efficiency and resiliency of NFIC-links are exploited in the context of a 3D NoC design. We demonstrate that overall reliability of the NFIC-enabled 3D NoC is significantly better compared to a conventional stand-alone TSV-based architecture.

Understanding the role of competition and cooperation among multiple interacting species of microorganisms that constitute the microbiome and decipher how they enforce homeostasis or trigger diseases requires the development of multi-scale computational models capable of capturing both intra-cell processing (i.e., gene-to-protein interactions) and inter-cell interactions. The multi-scale interdependency that governs the interactions from genes to proteins within a cell and from molecular messengers to cells to microbial communities within the environment raises numerous computation and communication challenges. Internal cell processing cannot be simulated without knowledge of the surroundings. Similarly, cell-cell communication cannot be fully abstracted without stated of internal processing and diffusion effects of molecular messengers. To address the computeand communication-intensive nature of modeling microbial communities, in this paper, we propose a novel reconfigurable NoC-based manycore architecture capable of simulating a large scale microbial community. The reconfiguration of the NoC topology is achieved through the fractal analysis of NoC traffic and use of the on-chip wireless interfaces. More precisely, we analyze the computational and communication workloads and exploit the observed fractal characteristics for proposing a mathematical strategy for NoC reconfiguration. Experimental results demonstrate that the proposed NoC architecture achieves 56.6 and 62.8 percent improvement in energy delay product over the conventional wireline mesh and flatten butterfly-based high radix NoC architectures, respectively.

A low power, 2×2 V-band beamforming receiver array using a local-oscillator (LO) phase-shifting approach is presented in this paper. Significant power savings in LO routing is achieved using an 8th sub-harmonic injection locked oscillator (SHILO), used for both frequency-multiplication and programmable phase-shift to implement beamforming. SHILO generates mm-Wave phase shift of ±90°. For low power, a low-noise amplifier (LNA) and mixer are operated using 1.3 V, while SHILO operates at only 0.5 V supply. The receiver is fabricated in TowerJazz 0.13 μm SiGe BiCMOS process and occupies total area of just 1×2 mm2. A single receiver consumes 11.4 mW power, with a peak gain of 8.23 dB, minimum noise figure (NF) of 7.7 dB, and 3-dB bandwidth of >11 GHz. The 2×2 array achieves a peak-to-null ratio of 21 dB.

The millimeter (mm)-wave small-world wireless NoC (mSWNoC) is an enabling interconnect architecture to design high performance and low power multicore chips. As the mSWNoC has an overall irregular topology, it is extremely important to design suitable deadlock-free routing mechanisms for it. In this paper we quantify the latency, energy dissipation, and thermal profiles of mSWNoC architectures by incorporating irregular network routing strategies. We demonstrate that the latency, energy dissipation, and thermal profile are affected by the adopted routing methodologies. In presence of the benchmarks considered, the variation in latency and energy dissipation is small. However, the network hotspot temperature can vary considerably depending on the exact routing strategy and the characteristics of the benchmark.

Continuing progress and unprecedented integration levels in current silicon technologies make possible complete end-user systems consisting of an extremely high number of cores integrated on a single chip for embedded or high-performance computing. However, without developing new paradigms for energy- and thermally-efficient design, meeting the computing, storage, and communication demands of the emerging applications is highly unlikely. Moreover, in order to sustain the predicted growth of number of embedded cores on a single die, it is extremely important to have a scalable, low power, and high bandwidth on-chip communication infrastructure. Towards this end, wireless Network-on-Chip (WiNoC) represents an emerging paradigm to design a low power yet high bandwidth interconnect infrastructure for multicore chips.

The millimeter-wave small-world wireless network-on-chip (mSWNoC) is an enabling interconnect architecture to design high-performance and low-power multicore chips. As the mSWNoC has an overall irregular topology, it is essential to design and optimize suitable deadlock-free routing mechanisms for it. In this paper, we quantify the latency, energy dissipation, and thermal profiles of mSWNoC architectures by incorporating irregular network routing strategies. We demonstrate that the latency, energy dissipation, and thermal profile are affected by the adopted routing methodologies. The overall system performance and thermal profile are governed by the traffic-dependent optimization of the routing methods. Our aim is to establish the energy-thermal-performance trade-offs for the mSWNoC depending on the exact routing strategy and the characteristics of the benchmarks considered.

Sensor networks have particularly important applications in challenging environments. However, those challenging environments also pose significant challenges to network sustainability and reliability. In such environments, the network often becomes disruptive and even unavailable during downtime. This results in undesired loss of valuable spatial-temporal sensor data. Data persistence can be achieved by using in-situ encoding and caching of data through distributed mechanisms. However, the existing methods in the literature are mainly based on network random walks, which not only incur significant communication overhead, but also are prone to network or node failures. In this article, we presentECPC, a distributedErasureCoding with randomizedPowerControl protocol for preserving data in disruptive sensor networks.ECPConly requires each sensor node to perform several rounds of broadcast in its neighborhood at some randomly chosen radio transmission power levels, and thus it incurs low communication overhead. We proved thatECPCachieves the expected code degree distribution and pseudo-global randomness of erasure coding principles. We have also evaluated the performance ofECPCby comparing it with several key related approaches in the literature (such as EDFC and RCDS). The performance comparisons validate that our proposedECPCprotocol can reach higher data reliability under varying node failure probabilities. In addition,ECPCprotocol is also shown to be scalable with different network sizes.

The Network-on-Chip (NoC) paradigm is used as a scalable interconnection infrastructure for multi-core chips. To enhance the performance of conventional interconnect-based multi-core chips, on-chip wireless interconnect has emerged as a radically different technology. However, this emerging interconnect paradigm imposes significant challenges pertaining to reliable integration and design. In this paper, we focus on two types of mm-wave wireless NoC architectures. One is a hierarchical architecture with long-range wireless shortcuts and the other is a power-law connectivity based small-world network without any hierarchy. We demonstrate that though the hierarchical architecture offers more bandwidth with lower energy dissipation than the small-world-based counterpart, it has significantly more area overhead. Also, the power-law connectivity based small-world wireless NoC is more robust in presence of wireless link failures.

An ultra-wideband low phase variation variable gain amplifier (VGA) in 0.18/am BiCMOS process with high linearity is presented in this paper. The proposed VGA uses novel current steering gain blocks to achieve gain steps with low phase variation. The VGA has a measured gain range of 6.3-8.1 dB over the entire frequency range of 12-40 GHz and shows a phase variation of 0.2-0.78 °/dB. The VGA achieves a simulated input P1dB of 0 dBm at 26 GHz while consuming only 20.5 mW from 1.5 V power supply and occupies an active area of just 0.05 mm2. The VGA shows 7.6 times better Figure of Merit as compared to current state-of-the-art VGAs.

In challenging environments, sensor networks may become disruptive even unavailable (downtime), resulting in data losses. In-situ encoding and caching data in a distributed fashion can preserve data persistence during downtime. However, the existing approaches are mainly based on random walks, which incurs significant communication overhead and may itself fail due to network disruptions. In this paper, we present a distributed Erasure Coding with randomized Power Control (ECPC) mechanism to preserve downtime data persistence in disruptive sensor networks. ECPC only requires each node to perform a single broadcast at each of its several randomly selected power levels. Thus it incurs low communication overhead. Moreover the storage space requirement is lower and uniform across the network. It applies randomized power control in localized data broadcast to achieve expected code degree distribution and ensure pseudo-global randomness for erasure coding. Performance comparisons between ECPC and other existing approaches show that ECPC mechanism can reach higher data reliability under varying node failure probabilities. In addition, our ECPC approach is scalable with network sizes.

The Network-on-chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing methods of implementing a NoC with planar metal interconnects are deficient due to high latency and significant power consumption arising out of multihop links used in data exchange. To address these problems, we propose design of a hierarchical small-world wireless NoC architecture where the multihop wire interconnects are replaced with high-bandwidth and single-hop long-range wireless shortcuts operating in the millimeter (mm)-wave frequency range. The proposed mm-wave wireless NoC (mWNoC) outperforms the corresponding conventional wireline counterpart in terms of achievable bandwidth and is significantly more energy efficient. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously further enhance the performance, and provide an energy-efficient solution for design of communication infrastructures for multicore chips.

Traditional many-core designs based on the Network-on-Chip (NoC) paradigm suffer from high latency and power dissipation as the system size scales up due to their inherent multi-hop communication. NoC performance can be significantly enhanced by introducing long-range, low power, and high-bandwidth single-hop wireless links between far apart cores. This paper presents a design methodology and performance evaluation for a hierarchical small-world NoC with CMOS compatible on-chip millimeter (mm)-wave wireless long-range communication links. The proposed wireless NoC offers significantly higher bandwidth and lower energy dissipation compared to its conventional non-hierarchical wired counterpart in presence of both uniform and non-uniform traffic patterns. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously provide an energy efficient solution for design of many-core communication infrastructures.

Massive levels of integration are making modern multicore chips all pervasive in several domains. High performance, robustness, and energy-efficiency are crucial for the widespread adoption of such platforms. Networks-on-Chip (NoCs) have emerged as communication backbones to enable a high degree of integration in multicore Systems-on-Chip (SoCs). Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multihop links with high latency and power consumption. This limitation can be addressed by drawing inspiration from the evolution of natural complex networks, which offer great performance-cost trade-offs. Analogous with many natural complex systems, future multicore chips are expected to be hierarchical and heterogeneous in nature as well. In this article we undertake a detailed performance evaluation for hierarchical small-world NoC architectures where the long-range communications links are established through the millimeter-wave wireless communication channels. Through architecture-space exploration in conjunction with novel power-efficient on-chip wireless link design, we demonstrate that it is possible to improve performance of conventional NoC architectures significantly without incurring high area overhead.

In a traditional Network-on-Chip (NoC), latency and power dissipation increase with system size due to its inherent multi-hop communications. The performance of NoC communication fabrics can be significantly enhanced by introducing long-range, low power, high bandwidth direct links between far apart cores. In this paper a design methodology for a scalable hierarchical NoC with on-chip millimeter (mm)-wave wireless links is proposed. The proposed wireless NoC offers significantly higher throughput and lower energy dissipation compared to its conventional multi-hop wired counterpart. It is also demonstrated that the proposed hierarchical NoC with long range wireless links shows significant performance gains in presence of various application-specific traffic and multicast scenarios.

A novel LC Quadrature VCO (QVCO) employing bottom-series coupling and capacitor tapping to suppress phase noise at low voltage operation is presented. Placing the coupling transistors at the bottom of the switching pairs, the bottom-series coupling method yields zero resonator-phase-shift (RPS) which maximizes the quality factor (Q) of the resonator. The capacitor tapping technique allows a large signal swing at the resonator outputs while maintaining the current sources and the turned-on switching transistors in saturation. Therefore, the signal-to-noise ratio (SNR) and the loaded Q of the resonator are both boosted resulting in a low phase noise. The proposed QVCO achieves the figure of merit (FOM) of 189 dBc/Hz with a phase noise of -120.3 dBc/Hz at 1-MHz offset when operating at 6 GHz, and draws 5 mA from a 1-V power supply.

An enhanced linearity improvement technique based on the third order intermodulation distortion cancellation or gm3 cancellation technique is presented in this paper. By identifying the issues related to the conventional gm3 cancellation method, the proposed technique is used to design a 0.18/spl mu/m CMOS LNA using Jazz semiconductor's BiCMOS process. With an IIP3 of more than +16dBm and gain of more than 15dB, the enhanced linearity LNA or EL2NA with a current consumption of 9mA from a 1.8V supply, provides an efficient way of improving linearity of 5G range direct conversion receivers.

This paper presents a new harmonic filtering technique to lower the phase noise of CMOS LC voltage-controlled oscillator (VCO) based on loaded-Q improvement approach. A single resistor was used at the drain node of the bias transistor instead of extra inductors and capacitors. The wide-band nature of resistance can suppress the second harmonic as well as other even harmonics leaking from the LC tank across the full period of oscillation, thus preserve the loaded quality factor of the LC tank. As a proof of concept, a completely integrated 5.3GHz all PMOS LC VCO was implemented in a 0.18mum BiCMOS process. The simulation result shows the achieved phase noise of -129.5 dBc/Hz at 1-MHz offset and -110 dBc/Hz at 100-KHz offset and -86 dBc/Hz at 10-KHz while the VCO core draws 5mA from a 1.8V supply. The circuit is being fabricated with Jazz semiconductor