EDBT 2026 Demo / reviewers in the wild / expert
Joshua Noseworthy
dblp:17/5319
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 2008
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Embedded and real-time systems · 50% Reconfigurable computing and FPGAs · 50% | |
| Computer networks
1 paper |
Physical-layer communications · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Reconfigurable computing and FPGAs
FPGA architecture |
0.1 | 1 | 2006 | Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic · FPGA 2006 |
Embedded and real-time systems › embedded processor
FPGA embedded processor |
0.1 | 1 | 2006 | Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic · FPGA 2006 |
Physical-layer communications
software-defined radio |
0.0 | 1 | 2006 | Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic · FPGA 2006 |
Methods — techniques the papers use, named apart from their topics
interface comparison · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2008 | Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGAabstractIncreasing device densities have prompted FPGA manufacturers, such as Xilinx and Altera, to incorporate larger embedded components, including multipliers, DSP blocks and even embedded processors. One of the recent architectural enhancements in the Xilinx Virtex family architecture is the introduction of the PowerPC405 hard-core embedded processor. In this paper we present a software defined radio application that serves as a vehicle for investigating effective communication between the PowerPC405 processor and the surrounding FPGA fabric. Joshua Noseworthy, Miriam Leeser |
IEEE Trans. Very Large Scale Integr. Syst. | 1 |
| 2006 | Efficient use of communications between an FPGA's embedded processor and its reconfigurable logicabstractAbstract — Increasing device densities allow chip manufacturers to integrate more functionality onto a single piece of silicon. FPGA manufacturers, such as Xilinx and Altera, use these additional resources to further diversify and improve the processing capabilities of their architectures. One of the more recent architectual enhancements that has been made to Xilinx’s Virtex family architecture is the introduction of the PowerPC405 hard-core embedded processor. In this paper we present a Software Defined Radio Application that serves as a vehicle for investigating effective communications between the PowerPC405 Processor and the surrounding FPGA fabric.. A challenging aspect of developing applications that target the PowerPC is the interfacing of the processor with the surrounding reconfigurable logic. We have implemented a dozen different versions of a Software Defined Radio (SDR) application to exercise the various interfaces that enable communication between the processor and the surrounding FPGA fabric. The implementations differ only in the interfaces used. Our results indicate that the performance of the SDR application application can be increased by as much as 60 percent just by choosing the interfaces that are most appropriate for the different types of data in the implementation. This demonstrates that the performance of FPGA applications that use the embedded processor are dramatically effected by the mechanisms chosen to enable communication between the processor and its surrounding resources. I. Joshua Noseworthy, Miriam Leeser |
FPGA | 1 |