EDBT 2026 Demo / reviewers in the wild / expert
Akio Niwa
dblp:17/5562
· DBLP profile ↗
2ranked-venue papers
2as first author
0since 2021 · last 1989
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 50% Processor architecture and microarchitecture · 50% | |
| Computer networks
1 paper |
Internet architecture and protocols · 100% |
Topics — the 1 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › microprogramming
microprogrammed control |
0.0 | 1 | 1986 | A 32-Bit Custom VLSI Processor for Communications Network Nodes · IEEE J. Sel. Areas Commun. 1986 |
Methods — techniques the papers use, named apart from their topics
hardware/software simulation · 0.0hardware-software simulation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1989 | Evolution of NTT's Networks Towards INS
Akio Niwa, Hiroshi Tokunaga |
Comput. Networks | 1 |
| 1986 | A 32-Bit Custom VLSI Processor for Communications Network NodesabstractAimed at the application to processors used in communications networks, three kinds of custom CMOS VLSI chips, each integrating approximately 10 kilogates, were developed. During the development of these chips, we overcame various restrictions on the VLSI design, such as input/output pin limitations, bug correction difficulty, and input/output signal delay. A combination of the software and hardware simulators efficiently eliminated logic errors. Microprogram control memory is placed externally to VLSI chips to facilitate tentative correction of possible remaining errors. Two types of processors sharing uniform architecture were also developed for an overall optimum cost-effectiveness using these VLSI chips. One uses all three kinds of VLSI chips and is suitable for switching and communications processing applications. The other includes one VLSI chip and consists of a single printed circuit board. It is suitable for a portable console processor or a processor imbedded in various equipment. These VLSI processors are being introduced in large numbers in communications networks in Japan. Akio Niwa, Takahiko Yamada |
IEEE J. Sel. Areas Commun. | 1 |