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Akila Gothandaraman

dblp:17/5638 · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 2011
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
GPUs and heterogeneous computing · 44% Performance modeling and evaluation · 22% High-performance computing · 13%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Performance modeling and evaluation › system-level analysis › architecture evaluation
accelerator comparison
0.112011
Comparing Hardware Accelerators in Scientific Applications: A Case Study · IEEE Trans. Parallel Distributed Syst. 2011
GPUs and heterogeneous computing
GPU computing
0.112011
Comparing Hardware Accelerators in Scientific Applications: A Case Study · IEEE Trans. Parallel Distributed Syst. 2011
GPUs and heterogeneous computing › heterogeneous programming models
OpenCL
0.112011
Comparing Hardware Accelerators in Scientific Applications: A Case Study · IEEE Trans. Parallel Distributed Syst. 2011
Reconfigurable computing and FPGAs
FPGA accelerator
0.112006
Poster reception - Reconfigurable accelerator for quantum Monte Carlo simulations in N-body systems · SC 2006
Emerging computing paradigms › quantum computing › quantum simulation
quantum monte carlo simulation
0.112006
Poster reception - Reconfigurable accelerator for quantum Monte Carlo simulations in N-body systems · SC 2006
High-performance computing › scientific computing
scientific computing application
0.012011
Comparing Hardware Accelerators in Scientific Applications: A Case Study · IEEE Trans. Parallel Distributed Syst. 2011
High-performance computing
n-body simulation
0.012006
Poster reception - Reconfigurable accelerator for quantum Monte Carlo simulations in N-body systems · SC 2006
High-performance computing
scientific computing
0.012006
Poster reception - Reconfigurable accelerator for quantum Monte Carlo simulations in N-body systems · SC 2006

Methods — techniques the papers use, named apart from their topics

performance evaluation · 0.1brook+ · 0.1VHDL · 0.1CUDA · 0.1pipelined hardware design · 0.1fixed-point representation · 0.1
YearPublicationVenuePosition
2011 Comparing Hardware Accelerators in Scientific Applications: A Case Study
abstract
Multicore processors and a variety of accelerators have allowed scientific applications to scale to larger problem sizes. We present a performance, design methodology, platform, and architectural comparison of several application accelerators executing a Quantum Monte Carlo application. We compare the application's performance and programmability on a variety of platforms including CUDA with Nvidia GPUs, Brook+ with ATI graphics accelerators, OpenCL running on both multicore and graphics processors, C++ running on multicore processors, and a VHDL implementation running on a Xilinx FPGA. We show that OpenCL provides application portability between multicore processors and GPUs, but may incur a performance cost. Furthermore, we illustrate that graphics accelerators can make simulations involving large numbers of particles feasible.
Rick Weber, Akila Gothandaraman, Robert J. Hinde, Gregory D. Peterson
IEEE Trans. Parallel Distributed Syst.2
2008 FPGA acceleration of a quantum Monte Carlo application
Akila Gothandaraman, Gregory D. Peterson, G. Lee Warren, Robert J. Hinde, Robert J. Harrison
Parallel Comput.1
2006 Poster reception - Reconfigurable accelerator for quantum Monte Carlo simulations in N-body systems
abstract
Recent advances in FPGA technology make them an attractive platform for accelerating scientific computing applications. We present a novel hardware accelerator for Quantum Monte Carlo simulations in N-body systems. The design is deeply pipelined and exploits the inherent fine-grained parallelism available using an FPGA for all calculations. The design is implemented on a Xilinx Virtex II Pro XC2VP30 device and preliminary results indicate a maximum operating frequency of 100MHz. A single instance of our design offers an estimated speedup of 20x and accuracy comparable to the serial code running on a 2.8GHz Intel Pentium 4 processor. This architecture performs all computations with fixed-point representation and delivers accuracy on the order of or better than double-precision floating point. After deploying a single instance on the present FPGA platform, targeting our design on the Cray XD1 platform with a high gate-density FPGA will allow us to operate multiple cores in parallel.
Akila Gothandaraman, G. Lee Warren, Gregory D. Peterson, Robert J. Harrison
SC1