A fresh look at the technical problems of present-day logic design and at the principal activities of the logic designer resulted in a system for hierarchical logic design. It is supported by a novel, high-level graphic language to describe the connections between logical devices. A major concern was to ensure that processes invoked by a user while designing, modifying and testing logic normally require only a few seconds or, on rare occasions, a few minutes to execute.

Computer Science bears approximately the same relationship to computers as Aerodynamics bears to sailboats. It describes how they work but has little impact on their design which is based almost entirely on intuition strengthened and controlled by experience. However, one day, the Wright brothers of the "ultra-computer" will get to their Kitty Hawk and Computer Science will come into its own. In preparation for that day stands the present volume. It is an excellent mathematics textbook written by an experienced teacher.

This paper demonstrates two improvements in coding techniques that could be used for memory word coding. First, within the fixed structure of a Hamming single-error-correcting, double-error-detecting (SEC/DED) code, an improvement can be obtained in circuit cost and operational speed over more conventional code implementations. Second, the mechanics of error correction in a fault-tolerant computer may be carried out via conventional hardware means or by use of the existing system facilities, such as the combination of the microprogram unit, local store, and the arithmetic-logic unit. These improvements may be obtained by the use of Rotational Coding schemes in conjunction with a technique calied "lookaside correction." This paper first shows a generalized algorithm for specifying the parity check matrix of Rotational Codes. The structure implemented by the parity check matrix in this paper is not merely encoding and decoding circuitry, but translates between Rotational Code forms and byte-parity encoded forms. The unique feature of these translators is that use of the Rotational Code permits the error correction to be performed on only a subset of the data word bits, and only if a single-error condition has been detected. The correction mechanism may be either a hardware logic circuit or firmware. The paper concludes with a comparison of the circuit requirements and correctional speed of the Hamming (72, 64) single-error-correcting, double-error-detecting code, as it normally would be implemented, and a Rotational Code translator also operating on 64 data bits and 8 check bits.

A method is given of designing a simple self-checking and self-testing decoder checking circuit which uses much less circuitry than previous checkers. An analysis is given of the circuit savings and of the probability of erroneous decoder operation before error detection.