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Eric Rachlin

dblp:17/6135 · DBLP profile ↗
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7ranked-venue papers
4as first author
0since 2021 · last 2012
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-authorArtificial intelligence and machine learning · 1Graphics, computer vision, multimedia, augmented reality and games · 1Theory of computation · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer graphics and multimedia
1 paper
Geometric modeling and processing · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Emerging computing paradigms · 77% Integrated circuit design · 23%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms › nanotechnology
nanoscale computing
0.112008
Analysis of Mask-Based Nanowire Decoders · IEEE Trans. Computers 2008
Geometric modeling and processing
shape alignment
0.012012
Coregistration: Simultaneous Alignment and Modeling of Articulated 3D Shape · ECCV (6) 2012
Integrated circuit design
digital circuit design
0.012008
Analysis of Mask-Based Nanowire Decoders · IEEE Trans. Computers 2008

Methods — techniques the papers use, named apart from their topics

optimization · 0.1coregistration · 0.1stochastic analysis · 0.1
YearPublicationVenuePosition
2012 Coregistration: Simultaneous Alignment and Modeling of Articulated 3D Shape
David A. Hirshberg, Matthew Loper, Eric Rachlin, Michael J. Black
ECCV (6)3
2008 A framework for coded computation
abstract
Error-correcting codes have been very successful in protecting against errors in data transmission. Computing on encoded data, however, has proved more difficult. In this paper we extend a framework introduced by Spielman [14] for computing on encoded data. This new formulation offers significantly more design flexibility, reduced overhead, and simplicity. It allows for a larger variety of codes to be used in computation and makes explicit conditions on codes that are compatible with computation. We also provide a lower bound on the overhead required for a single step of coded computation.
Eric Rachlin, John E. Savage
ISIT1
2008 Analysis of Mask-Based Nanowire Decoders
abstract
Stochastically assembled nanoscale architectures have the potential to achieve device densities 100 times greater than today's CMOS. A key challenge facing nanotechnologies is controlling parallel sets of nanowires (NWs), such as those in crossbars, using a moderate number of mesoscale wires. Three similar methods have been proposed to control NWs using a set of perpendicular mesoscale wires. The first is based on NW differentiation during manufacture, the second makes random connections between NWs and mesoscale wires, and the third, a mask-based approach, interposes high-K dielectric regions between NWs and mesoscale wires. Each of these addressing schemes involves a stochastic step in their implementation. In this paper, we analyze the mask-based approach and show that, when compared to the other two schemes, a large number of mesoscale control wires are necessary for its realization.
Eric Rachlin, John E. Savage
IEEE Trans. Computers1
2008 Nanowire addressing with randomized-contact decoders
Eric Rachlin, John E. Savage
Theor. Comput. Sci.1
2006 Nanowire addressing with randomized-contact decoders
abstract
Methods for assembling crossbars from nanowires (NWs) have been designed and implemented. Methods for controlling individual NWs within a crossbar have also been proposed, but implementation remains a challenge. A NW decoder is a device that controls many NWs with a much smaller number of lithographically produced mesoscale wires (MWs). Unlike traditional demultiplexers, all proposed NW decoders are assembled stochastically. In a randomized-contact decoder (RCD) (Hogg et al., 2006), for example, field-effect transistors are randomly created at about half of the NW/MW junctions. In this paper, we tightly bound the number of MWs required to produce a correctly functioning RCD with high probability. We show that the number of MWs is logarithmic in the number of NWs, even when errors occur. We also analyze the overhead associated with controlling a stochastically assembled decoder. As we explain, lithographically-produced control circuitry must store information regarding which MWs control which NWs. This requires more area than the MWs themselves, but has received little attention elsewhere
Eric Rachlin, John E. Savage
ICCAD1
2006 Radial addressing of nanowires
abstract
We introduce radial encoding of nanowires (NWs), a new method of differentiating and controlling NWs by a small set of mesoscale wires for use in crossbar memories. We describe methods of controlling these NWs and give efficient manufacturing algorithms. These new encoding and decoding methods do not suffer from the misalignment characteristic of flow-aligned NWs. They achieve comparable effective pitch and resulting memory density with axially encoded NWs, while avoiding potential cases of address ambiguity and simplifying NW preparation. We also explore hybrid axial/radial encodings and show that they offer no net benefit over pure codes.
John E. Savage, Eric Rachlin, André DeHon, Charles M. Lieber
ACM J. Emerg. Technol. Comput. Syst.2
2005 Evaluation of design strategies for stochastically assembled nanoarray memories
abstract
A key challenge facing nanotechnologies is learning to control uncertainty introduced by stochastic self-assembly. In this article, we explore architectural and manufacturing strategies to cope with this uncertainty when assembling nanoarrays, crossbars composed of two orthogonal sets of parallel nanowires (NWs) that are differentiated at their time of manufacture. NW deposition is a stochastic process and the NW encodings present in an array cannot be known in advance. We explore the reliable construction of memories from stochastically assembled arrays. This is accomplished by describing several families of NW encodings and developing strategies to map external binary addresses onto internal NW encodings using programmable circuitry. We explore a variety of different mapping strategies and develop probabilistic methods of analysis. This is the first article that makes clear the wide range of choices that are available.
Benjamin Gojman, Eric Rachlin, John E. Savage
ACM J. Emerg. Technol. Comput. Syst.2