With the emergence of large-scale, high-frequency modular converters, high-performance distributed control systems (DCSs) are receiving increasing attention. These systems demand both high-data-rate communication and low synchronization error (SE). Xilinx Aurora, an interface Intellectual Property (IP), supports multi-gigabit data rates but lacks timing distribution capabilities. This paper proposes Synchronous Aurora (Sync-A), an enhanced Aurora-like IP that implements White Rabbit (WR)-based synchronization techniques on top of the existing Xilinx Aurora IP, achieving both multi-gigabit data rates and sub-nanosecond SE timing distribution. The operating principles of WR and the implementation of WR-based synchronization techniques in the Sync-A IP are explained in detail. An overview of the proposed IP is presented to highlight its ease of use. Experimental results validate its performance.

The implementation complexity of space vector modulation (SVM) significantly increases in multi-level converters, rendering the SVM an onerous task, if not impossible, in such systems. On the other hand, developed SVMs for multilevel converters achieve modulation objectives such as reducing common-mode voltage and switching loss, harmonic suppression, etc., focusing on a particular topology with limited applicability to other converter configurations. This paper tackles the mentioned challenge by proposing a generalized SVM adaptable to all three-phase converters. The algorithm takes advantage of repetitive patterns in multi-level converters to eliminate the additional computational effort while still achieving modulation objectives other than only providing switch commands as far as generality is not compromised. In the proposed SVM, no look-up table is employed, minimum switching loss is guaranteed, and 33% less switching is achieved as not three phases ever switch during any time interval, and one phase remains constant while the other two switch. A dc-link and flying capacitor voltage balancing algorithm is also introduced, and the properness of the SVM is shown for a five-level active neutral point clamped (ANPC) inverter; results are compared to those from carrier-based modulation techniques, and the superior operation of the proposed SVM is proved.

With the emergence of multilevel converters, distributed control systems (DCSs) are becoming increasingly popular due to their scalability, modularity, and flexibility. However, DCSs present a significant challenge: synchronization among controllers, particularly when implementing advanced control schemes. Ultra-precise synchronization requires the concurrent realization of frequency, time, and phase synchronization. This paper gives an overview of FPGA-based synchronization techniques covering all three subcategories, including: 1) clock-sharing-based and clock-recovery-based frequency synchronization, 2) Precision Time Protocol (PTP)-based time synchronization, 3) White Rabbit Network (WRN)-based phase synchronization. The operating principles, FPGA implementation, and experimental results of these techniques will be discussed.

Selective harmonics elimination (SHE) is employed to effectively mitigate specific low-order harmonics in low switching-frequency converters by precisely manipulating switching angles within a line cycle. SHE relies on a steady-state solution, raising questions about its dynamic performance and impact. This paper focuses on the small-signal characterization of SHE and its influence on converter impedance. It was observed that SHE has an amplifying—and uncontrolled—effect on certain high-frequency points, particularly pronounced when utilizing input voltage feedforward control due to its direct perturbation path. This leads to the converter terminal impedance exceeding 90°, violating the Passivity Criterion. A potential solution to mitigate this impact is to update the angle and modulation index of the SHE schemes at a slower rate or to avoid the use of feedforward terms. Alternatively, switching to SPWM-type modulation schemes optimized for low switching frequency operation may be considered.

Electric machines are sensitive to parameter variations and faults, which manifest as long-term or abrupt changes, gradually leading to a loss of regulation if neglected. Detecting and identifying them is crucial for ensuring these machines’ robust performance and reliability, especially for electromagnetic parts, which are more implicit and difficult to detect than mechanical parts. This paper explores a dq-axis frequency-sweeping approach to construct the terminal-behavior model, which analyzes the electrical interface’s input small-signal response. The response is later decoupled from the source output impedance and mechanical load input impedance to obtain an un-terminated model by suppressing load torque oscillation. The electrical terminal-behavior of healthy and faulty machines is captured as frequency response functions, which can be used for real-time detection of parameter variations or faults. A mapping between the un-terminated electrical terminal-behavior models and various faulty or parameter-varying cases can be established by systematically sweeping through different fault conditions and operating points. Simulation results are presented to demonstrate the validity and practicability of this approach, especially for inter-turn short-circuit faults. The interior permanent magnet synchronous motor (IPMSM) is used as an example, but the method is extendable to other types of motors.

Power semiconductor devices play an important role in circuit breakers (CB) to provide fast, arc-less, fault current interruption in dc distribution systems. Series connection of power devices is often used to increase the breaker voltage rating for application in medium voltage dc systems. This paper presents a low-cost gate driver circuit based on passive components which can achieve gate control of the series power device stack using only a single isolated gate driver IC. The circuit provides reliable coupling of the CB logic control signal while achieving a balanced device voltage distribution during the fault turn-off event. Transient voltage suppression (TVS) diodes are utilized to limit the turn-off voltage of the power devices and provide the current return path for the gate capacitor discharge of the upper device(s). Simulation and experimental results are provided to verify circuit operation in a dc solid state circuit breaker system.

Modular power converters in combination with distributed control architecture has been promising in medium-voltage applications due to its modularity and scalability. The requirement of the synchronization accuracy is elevated dramatically for the communication network with advanced distributed control schemes. This paper presents a phase-locked loop (PLL)-based synchronization method with sub-ns synchronization accuracy based on the White Rabbit protocol. Digital perturbation injection method is proposed to estimate the PLL closed-loop characteristics, and the PLL stability is analyzed. Good agreements of the closed-loop transfer function and stability analysis have been achieved between the theoretical calculation and experimental results. A four-PEBB 6kV SiC-based converter is established to verify the distributed communication and control system.

Impedance-based stability criterion has been proven to be a powerful tool for small-signal stability analysis and design, derived from Nyquist stability criterion and first developed in dc-dc power electronics converter systems. Recently it has been extended to ac systems to address the issues and challenges coming with more and more power electronics based converters connected to the existing ac power grids, either in transmission or distribution level. With that, only terminal information is sufficient to judge small-signal stability, which can be from either impedance model or experimental results. Therefore, internal details of inverters are not necessary, facilitating the system operator to integrate. This paper specifically presents a case study with multiple STATCOMs in IEEE 14-bus system to illustrate the application of the d-q frame impedance-based stability criterion. It shows that the impedance-based stability criterion can predict the small-signal stability with accurate oscillatory frequency for STATCOMs' interactions, and a new instability pattern was found from the impedance point of view.

Small-signal models of impedances for grid-tied converters have recently attracting researchers' attention and shown of great importance in stability analysis. This paper proposes the impedance model in d-q frame for STATCOMs, including dynamics from synchronization, current and voltage loops and reveals the significant features compared to other types of grid-tied converters that the 1) grid impedance should be taken into account because of regulated point of common coupling voltage, 2) full impedance matrix due to nearly zero power factor and 3) flipped polarity of impedances at low frequency as a result of inversed direction of reactive power. All these characteristics render difficulty in applying stability criterion. The model was verified experimentally with a scaled-down STATCOM prototype.

This paper proposes and designs a switching cell using paralleled gallium nitride (GaN) high-electron-mobility transistor (HEMTs) in the minimized, symmetric power and gate loops. Based on the design, 1Ω gate resistor was successfully applied to speed up the switching transient. The switching cell can be easy to replace on the mother board thanks to the pluggable connector and the cell owns unique heat sinks controlling its airflow, which enables effective heat dissipating. The switching cell design is also generalized for four GaN devices in parallel. The double pulse test was performed to evaluate the switching loss of the two/four paralleled 650V/60A GaN devices, and the commutation between the paralleled devices was analyzed based on the experimental waveforms. The experimental results on the LLC resonant converter using the designed switching cell, switching with up to 500 kHz switching frequency, are presented with 98% peak efficiency and 130W/in3power density.

This paper presents a complete design procedure for a motor drive aiming at maximizing nominal power within loss (30 W) and form factor (60 inch3) constraints. Particularly, this motor drive system has EMI requirement on both input and output sides and it should be free convection cooled. Loss-size Pareto fronts of multiple three-phase topologies including two-level voltage source converter (VSC), three-level neutral point clamped (NPC) converter, T-type converter and three-phase capacitor-decoupled triangular conduction mode (TCM) converter are explored in order to find the optimized design. Pareto fronts under different power level shows a maximum of 5 kVA power could be achieved by T-type converter within given limits and requirements. T-type converter is accordingly selected and constructed. A power density of 80 W/inch3is achieved by the prototype. Finally, experimental results obtained with the free convection cooled converter prototype are presented for validating purposes, demonstrating the 99.2% efficiency (42.3 W loss) at nominal load.

This paper presents some of the key advances in power electronics pertaining to shipboard electric power system applications. The focus is on the emerging wide bandgap semiconductor devices, i.e., silicon carbide (SiC) and gallium nitride (GaN) devices, and their potential impact on future shipboard power conversion and drives. Their benefits on power converter efficiency and power density are explained through a case study of a medium-voltage (MV) class motor drive system. SiC and GaN also enable new applications, including solid-state transformers, while posing new design and application challenges such as gate drive, protection, and interaction with loads. In addition to device related topics, this paper also overviews other important advances in power electronics, including topology, control, passive components, thermal management, filters, and packaging. The significance of power electronics building blocks (PEBBs) concept for shipboard power system development is discussed. Recognizing the growing complexity of shipboard power systems, some system-level technologies related to future MV direct current (dc) system architecture are highlighted.

This paper analyzed operation characteristics of 5L-ANPC converters under device open failure conditions and proposed fault tolerant control schemes for single and multiple device open failures. Simulation results validated the analysis and control schemes, which allow the converter to continue operating to provide balanced three-phase currents during fault tolerant operation.

This paper investigates the design procedure of cascaded H-bridge (CHB) and modular multilevel converter (MMC) topologies for medium-voltage and high-power industrial motor drive application. The design is performed using 1.7-kV insulated gate bipolar transistor (IGBT) technology. A model is derived for multi-pulse transformer to take into account its leakage parameters' effect on converter design. Also a comparison is done between MMC and CHB topologies at three different voltage levels: 4.16-, 6.9- and 13.8-kV and three different power levels: 1-, 3- and 5-MVA Comparison is done from several points of view like capacitance requirements, diode front-end and inverter stage losses, semiconductor rating and junction temperature and parts count.

An active power filter implemented with three single-phase Neutral Point Clamped (NPC) converters is presented and analyzed. The proposed active power filter is aimed to compensate current harmonics and reactive power in three-phase medium voltage power distribution systems. A predictive control algorithm provides the switching states that ensure fast current tracking capability. To take advantage of the predictive control implementation simplicity, this paper includes useful information to replicate this implementation on similar topologies of multilevel converters. The proposed scheme presents lower line to line voltage harmonic distortion as well as an independent control in each phase, compared with the conventional three-phase NPC topology. Simulated results confirm the implementation viability of the proposed active power filter topology and associated control strategy.

This paper proposes a detailed step-by-step design procedure for the input and output EMI filter of a matrix converter (MC) driving a 30 kW permanent magnet synchronous motor. The procedure involves modeling the EMI source and conduction path in the frequency domain, the design of the passive components, and the estimation of the EMI filter weight and volume. Finally, a weight comparison between the MC and alternative two- and three-level back-to-back converters is presented showing the significant advantage offered by the MC in this regard; namely a 30 % and 50 % lower weight than its three-and two-level counterparts. Time and frequency domain simulations are used for verification purposes.

Modular multilevel converter is a next generation multilevel converters for medium to high voltage conversion applications, such as medium voltage motor drive and high voltage direct current transmission. One potential issue of this type of converter is the AC circulating current, which increases the current stress and brings additional conduction loss to the system. This paper proposes modified control architecture for modular multilevel converters, aiming at suppressing the AC components in the circulating current. Specifically, a proportional-resonant type minor loop is incorporated to regulate the most AC components of the circulating current to zero in addition to the DC regulation loop. The proposed minor loop can also be applied to single phase MMC, which is not available in previous methods. Simulation results for a three-phase MMC operating as an inverter are provided to demonstrate the feasibility of the proposed method.