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Piet Stevens

dblp:17/6222 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1983
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 72% Performance modeling and evaluation · 22% Integrated circuit design · 6%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
circuit simulation		 0.011983
Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Electronic design automation › hardware verification and test
logic simulation		 0.011983
BIMOS, an MOS oriented multi-level logic simulator · DAC 1983
Performance modeling and evaluation
simulation		 0.011983
BIMOS, an MOS oriented multi-level logic simulator · DAC 1983
Electronic design automation › circuit simulation
switch-level simulation		 0.011983
Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Electronic design automation › timing analysis
delay modeling		 0.011983
Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Integrated circuit design › digital circuit design
MOS circuits		 0.011983
BIMOS, an MOS oriented multi-level logic simulator · DAC 1983

Methods — techniques the papers use, named apart from their topics

time wheel · 0.0multi-level logic simulation · 0.0local relaxation · 0.0event-driven simulation · 0.0
YearPublicationVenuePosition
1983 BIMOS, an MOS oriented multi-level logic simulator
Piet Stevens, Guido Arnout
 DAC1
1983 Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling
abstract
In this paper a new algorithm for switch level simulation is presented. The algorithm is compatible with classical time wheel mechanisms for logic simulation and therefore allows for assignable delay modeling also at the switch level. The key to this algorithm is a local relaxation method which takes care of localized bilateral effects. The algorithm is shown to be 0(n) and proven to converge to a unique solution.
Dundar Dumlugol, Hugo De Man, Piet Stevens, Guido G. Schrooten
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3