As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficient methodology for system verification because of its fast simulation speed. The cycle-based simulation has a limitation in using asynchronous clocks that causes inherent cycle errors. In order to reuse the output of a C-level cycle-based simulation for the verification of a lower level model, the C-level model should be cycle-accurate with respect to the lower level model. In this paper, a cycle error correction technique is presented for two asynchronous clock models. An example design is devised to show the effectiveness of the proposed method. Our experimental results show that the fast speed of cycle-based simulation can be fully exploited without sacrificing the cycle accuracy.

Circuits containing functional blocks (modules) whose implementation details are not available pose major problems for delay fault testing. High-level testing methods are needed, but they often generate excessively large test sets to ensure good realization-independent fault coverage. This paper extends high-level delay fault models to large modular logic circuits by demonstrating that a hierarchical approach to delay test generation for modular circuits is feasible. Module implementation and input pattern pair requirements for robust delay testing are proposed along with a new fault model, the module path delay fault (MPDF) model. A test generation program called Module PATH delay test generator for MPDFs is presented, which exploits binary decision diagrams to increase its efficiency. Experimental results evaluating the proposed technique are presented, which show that it achieves a significant reduction in test set size compared to nonhierarchical approaches.