Recent research has developed a new, entirely digital architecture, called X-ORCA, that determines the phase shift of two periodic signals with a resolution as good as about 20 ps. This paper incorporates the X-ORCA system into a wireless experimental setup to form a localization system. The practical experiments utilize a 2.484 GHz transmitter and run the X-ORCA core on a Cyclone II FPGA. The results indicate that this simple localization system easily yields a spatial resolution in the sub-millimeter range.

Normally, research on evolutionary computation applies its algorithms to the solution or optimization of some technical or mathematical problems. But for some technical tasks, such as localization, nature seem to provides optimal solutions. This paper discusses how the barn owl auditory system can be conceptually realized on a digital system, such as a field programmable gate array. This adapted system yields a time resolution as small as 20 ps, even though it is clocked at only 85 MHz, which corresponds to a duty cycle of about 12 ns. The system achieves this result by copying the natural role model's core principles, i.e., employing a large number of simple, slowly operating processing elements, which are all connected to two passive wires, which induce only a very small additional time delay; these properties are the result of a natural evolutionary process that has taken millions of years.

The nucleus laminaris of the barn owl auditory system is quite impressive, since its underlying time estimation is much better than the processing speed of the involved neurons. Since precise localization is also very important in many technical applications, this paper explores to what extent the main principles of the nucleus laminaris can be implemented in digital hardware. The first prototypical implementation yields a time resolution of about 20 ps, even though the chosen standard, low-cost device is clocked at only 85 MHz, which leads to an internal duty cycle of approximately 12 ns.

Field-programmable gate arrays provide a very flexible implementation platform that supports the development of tamper-proof networked embedded systems. In order to achieve a secure mode of operation, many of these systems employ keyed-hash message authentication code, to provide security against intentional tampering. Since this algorithm is of high computational complexity, this paper utilizes various hardware-software co-design techniques for its implementation, and compares the results to standard software. The considered techniques vary in the degree of required design expertise and of how (software) functionalities are implemented in hardware logic.

Field-programmable gate arrays provide a flexible and easy-to-configure implementation platform that supports the development of tamper-proof networked embedded systems. Many of these systems employ the Advanced Encryption Standard algorithm in order to achieve a secure mode of operation. Since this algorithm is of a high computational complexity, this paper utilizes various hardware-software co-design techniques for its implementation. These techniques vary in the degree of required design expertise, the degree of how (software) functionalities are implemented in hardware logic, and the achievable speedup, which is about 12 to approximately four thousand.