Q-modules are internally clocked modules that can be used to satisfy delay-insensitive specifications. A single delay element is required with a one-sided bound that its value be greater than the maximum delay of the combination logic. Prototypes of components to implement Q-modules have been designed, and a design aid program, QSYN, to place instances of these components, personalize a PLA, and generate a MAGIC or CIF file for a CMOS realization, including the delay circuitry, is being developed. Testability is one of the advantages of Q-modules over clock-free delay-insensitive modules; circuitry is included in the cells for testing the logic and interconnections.>

A logic network is modeled with logic elements and a set of junctions formed by the interconnection of logic element pins. Electrical models for logic element pins are developed that include appropriate current and voltage parameters, and a consistent set of nomenclature for these parameters is introduced. An algorithm is then presented that can be used to determine the ability of ap element pin to force its junction to one or both of its valid logic states. The junctions may include bidirectional logic elements and wired-high and wired-low configurations. The algorithm evaluates every junction in the network and produces both error (fatal failure) and warning (possible failure) messages for each junction. This can be viewed as a "loading check" on the network. The noise margin for each junction is also computed and compared to a preselected value. Examples of the application of this algorithm on practical TTL circuits are presented.