This paper presents a set of algorithms for mapping sequential circuits onto look-up table based FPGAs and explores how it is possible to reduce the time delay and simplify the final routing results of this mapping. We define several new terms which are used to describe the problem. This work focuses on the mapping of flip-flops and their adjacent combinational parts in sequential circuits using LUT based FPGAs.

Run-time alias disambiguation (RTD) has been proposed as a technique for pointer aliasing. This paper suggests several RTD approaches which may be used for DOACROSS scheduling to exploit coarse-grained parallelism. We analyze the rerollability problem in the transformation of those RTD approaches to software pipelining in order to exploit the instruction level parallelism available in loops. Finally, we give some suggestion as to how to address the rerollability problem.

Compile-time code transformations which expose instruction-level parallelism (ILP) typically take into account the constraints imposed by all execution scenarios in the program. However, there are additional opportunities to increase ILP along some execution sequences if the constraints from alternative execution sequences can be ignored. Traditionally, profile information has been used to identify important execution sequences for aggressive compiler optimization and scheduling. The paper presents a set of static program analysis heuristics used in the IMPACT compiler to identify execution sequences for aggressive optimization. The authors show that the static program analysis heuristics identify execution sequences without hazardous conditions that tend to prohibit compiler optimizations. As a result, the static program analysis approach often achieves optimization results comparable to profile information in spite of its inferior branch prediction accuracies. This observation makes a strong case for using static program analysis with or without profile information to facilitate aggressive compiler optimization and scheduling.>