We use electrospinning to fabricate sperm-shaped magnetic microrobots with a range of diameters from 50 μm to 500 μm. The variables of the electrospinning operation (voltage, concentration of the solution, dynamic viscosity, and distance between the syringe needle and collector) to achieve beading effect are determined. This beading effect allows us to fabricate microrobots with similar morphology to that of sperm cells. The bead and the ultra-fine fiber resemble the morphology of the head and tail of the sperm cell, respectively. We incorporate iron oxide nanoparticles to the head of the sperm-shaped microrobot to provide a magnetic dipole moment. This dipole enables directional control under the influence of external magnetic fields. We also apply weak (less than 2 mT) oscillating magnetic fields to exert a magnetic torque on the magnetic head, and generate planar flagellar waves and flagellated swim. The average speed of the sperm-shaped microrobot is calculated to be 0.5 body lengths per second and 1 body lengths per second at frequencies of 5 Hz and 10 Hz, respectively. We also develop a model of the microrobot using elastohydrodynamics approach and Timoshenko-Rayleigh beam theory, and find good agreement with the experimental results.

A hybrid Time to Digital Converter (TDC) - Bang Bang (BB) All Digital Phase Locked Loop (ADPLL) architecture is proposed to optimize power, area, lock time, and design complexity. The Hybrid ADPLL architecture utilizes a low resolution two synthesizable Time to Digital Converters to achieve fast lock time, and then switches to a Bang-Bang like architecture once it is in the locked state. Such hybrid architecture enables the ADPLL to achieve lock time in less than 1 μ sec using an adaptive proportional derivative digital loop filter while consuming a power of 5.1 mW when locked at 4GHz with 1.37 ps rms period jitter. Additionally, The proposed ADPLL utilizes a novel power gated digitally controlled oscillator to power minimum number of transistors once the ADPLL is locked in a specific frequency band. The ADPLL occupies a total area of 85×150 μm2when synthesized on TSMC 65nm.

This paper presents a low-power, reduced-area finite field multiplier over GF(2m) for ultra-low-power devices. The proposed design supports any field GF(2m) with low-weight irreducible polynomial. The different implementations presented in this paper support 99% of fields with prime m1024, and all standard elliptic curves consuming 28.7μW and 4μW respectively, using the TSMC 65nm technology library. The design is demonstrated to operate at frequencies up to 500 MHz, allowing various trade-offs between power, energy and performance. The proposed design is shown to use around 40% less area and 40% less power than the other designs proposed in the literature. Hence, it enables implementing more secure ciphers for almost the lower cost than other available designs.

This paper introduces a novel 2T2M memristor based memory cell which, offers higher stability and noise margins than previous works. The proposed 2T2M RRAM module is similar to conventional 6T SRAM module in terms of delay and number of interface pins. However, the predicted area of the proposed 2T2M RRAM cell is significantly lower compared to the CMOS based 6T SRAM cell, and is also expected to consume lower energy. The nonvolatile characteristics of the cell make it more attractive for nonvolatile random access memory design. Write, read and repeated read operations of the proposed 2T2M RRAM cell are briefly explained. A complete RRAM module array based on the proposed 2T2M cell is designed, and the schematic details of the IO circuit is shown. A comparison between the proposed 2T2M cell and previous works is presented.

This paper proposes a new architecture that multiplexes both data and clock on serial links, reduces Inter symbol interference (ISI) by using a resistive termination technique, and uses two-level Manchester encoding to solve the reduced swing problem and enable the use of power efficient circuitry. Using this signaling scheme makes the system insensitive to jitter accumulation along the transmission line, and avoids the need for a power hungry clock and data recovery (CDR) circuit. A self-calibrating digital-delay line is also implemented inside the decoder to enable the system to operate efficiently across process, voltage and temperature variations. The proposed scheme is implemented for a 3mm long on-chip transmission line in TSMC 65nm technology and simulation results are presented.

This paper presents a variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers. The proposed design generates the 3-level signal without a ½VDD driver, thus removing all the overhead and hassle of an additional supply. Moreover, the proposed all-digital scheme uses half the clock frequency while maintaining the same data rate of the conventional scheme. As a result, the proposed design is much more robust across all possible variations. The transceiver is designed for a 3mm long lossy on-chip differential interconnect in TSMC 65nm CMOS technology. The transmitter serializes the parallel 1.9375Gbps 8-bit, then multiplexes it with the 15.5GHz clock to generate the three level signal on the differential TL, and a simple RX detects both the data and the clock from the signal.

This paper presents a modified design for a self-timed SerDes transceiver that was recently published [1]. The new architecture overcomes the main problems that arise in [1], while offering the same advantages. Resistive termination is used instead of source matching to eliminate the need for Manchester coding in [1], this resistive termination increased the data rate to be 16Gbps compared to 12Gbps in [1]. Moreover, resistive termination removed the limitation on the minimum operating frequency that existed in [1], solving a lot of problems at the slow process corners. A single ended transmission line is used instead of the differential transmission line in [1]. A calibration circuit is implemented to control the switching threshold of the detector at the receiver side to account for voltage and process variations. The SerDes transceiver is implemented for a 3mm long on-chip transmission line in 65nm TSMC CMOS technology, which is the same as [1]. The total power consumed in the Tx/Rx pair with the transmission line is 18.1mWatt, compared to 15.5mWatt in [1]. The proposed architecture have the same advantages in [1] of being self timed, eliminating the need for complex power hungry blocks such as Clock and Data Recovery (CDR) at the receiver, and being insensitive to jitter accumulated during transmission.

In this paper, a compact, reconfigurable, low-power mixed-signal neural front-end is presented. It employs a multi-bit ΣΔ DAC and a flexible digital filter in the feedback to suppress electrode DC offset up to ±50 mV. A low noise neural amplifier is used to amplify both spikes and local field potentials (LFPs). A second order gm-C anti-aliasing filter is used to filter out ΣΔ DAC quantization noise. A 8b 200 kS/s SAR ADC is proposed with 48.7 SNDR and 22.5 fJ/conv. step. The whole neural front-end achieves a low input-referred noise of 5.2 μVrmsfor a signal bandwidth of 10 kHz using a compact and highly programmable architecture. It consumes 6.4 μW from 0.8 V supply while occupying 0.049 mm2in 0.13 μm CMOS.

This paper presents the design and the implementation of a low power bang-bang all digital phase locked loop (BBADPLL). The design of the proposed architecture is based on the programmable coefficients of the digital loop filter (DLF) that manages the tradeoffs between stability and jitter of a closed loop. A proposed simple digital controlled oscillator (DCO) based on three stages ring oscillator provides a wide frequency range, and proven to be of lower area and power compared to arrayed DCO. The proposed design results in a significant reduction in the area and power compared to other time-to-digital converter (TDC) based ADPLL architectures. This reduction results from eliminating the need for complex, power, and area consuming TDC block, and arrayed DCO. A counter-based frequency acquisition loop using a binary search algorithm reduced the lock-in time significantly compared to similar work. The proposed BBADPLL architecture was implemented on TSMC CMOS 65nm technology with a frequency range 5–10GHz and a frequency resolution equals to 500MHz. The lock-in time is 2.4µs. The peak-to-peak period jitter and the RMS jitter at 10GHz are 1.49ps and 0.19ps, respectively. The total power consumed at 10GHz is only 2.7mWatt and the total area of the proposed ADPLL is 4372µm2, which is very small compared to other published architectures.

A process and temperature variation calibration scheme is proposed in this paper. The proposed system uses the supply voltage and body bias to calibrate the device parameters to match those of a certain process corner that is determined by the system designer. This scheme is characterized by its ability to dynamically change the desired mapping target according to the computational load. Moreover, the proposed system provides the ability to detect and control the n- and p-type variations independently through the use of an all-n and all-p ring oscillators. The calibration system has been implemented and simulated in TSMC 90-nm technology. Simulation results show that the system was able to reduce frequency spread (sigma) from 75 MHz to an average of 10 MHz and frequency variations from 34% to 3.1%. The results also show the system's ability to compensate for dynamic load variations.

In this paper, a new self-timed signaling technique for reliable low-power on-chip SerDes (Serialization and DeSerialization) links is presented. The transmitter serializes 8 parallel bits at 1.5GHz, and multiplexes the 12Gbps serial data stream with a 24GHz clock on a single line using three level signaling. This new signaling technique enables the receiver to recover the clock from the data with a simple phase detector circuitry. Moreover, this technique is insensitive to jitter accumulated during signal propagation or at the receiver input because the clock signal is extracted from the multiplexed data stream. Hence, timing errors in the received signal reflects in both the data and the extracted clock, and the data will be sampled correctly. The SerDes transceiver was implemented for a 3mm long lossy on-chip differential transmission line in 65nm TSMC CMOS technology. A primary advantage of building an all digital SerDes transceiver is the ease of scaling with technology, and the power and area reduction. The total power consumed in the Tx/Rx pair with the transmission line is 15.5mWatt, which is very small as compared to similar published signaling architectures.

On-chip serial link buses have been previously proposed as a strong solution to reduce the complexity and/or the energy dissipation of on-chip interconnect fabrics. However, it was noticed that serializing m-bits on a single interconnect (serial-link) increases the overall data switching activity. This paper presents a quantitative analysis of the switching activity of serial links, and provides closed form expressions for the average activity factors. Two transition encoding schemes, to reduce the activity factor of serial links, are discussed and analyzed. The impact of the encoding schemes on the MCF between neighboring interconnects is also discussed. The analysis shows that both of the schemes provide significant reduction in the average activity factor and energy dissipation reduction, but each in a different range of input activity factors. The two encoding bus schemes were modeled in a 70nm CMOS technology, and compared to an unencoded serial link bus and a parallel line bus. Simulation results show that the transition encoded bus schemes reduce the overall energy dissipation of the unencoded serial link bus by up to 96%

Insertion of time-borrowing (TB) flip-flops in multi-cycle repeater-based on-chip interconnects enables significant improvements in mean performance and energy by averaging systematic and random within-die (WID) delay variations across multiple interconnect segments. A statistically-based analytical model is derived to design a TB N-cycle interconnect with optimal delay variation tolerance. The model elucidates the dependency of the transparency window required to achieve data delay averaging on the delay variation mismatch between interconnect segments. Statistical circuit simulations and analyses in a 65nm process technology demonstrate that TB multi-cycle interconnects enable a 4-6% mean maximum clock frequency (FMAX) improvement and a corresponding 10% average energy savings over optimally designed multi-cycle interconnects with conventional master-slave flip-flops. The maximum mean FMAX benefit ranges from 4.0-7.5%, corresponding to approximately a bin-split shift in the FMAX distribution. For 1.41X larger WID delay variations, the maximum mean FMAX gain rises to 5-10%.

Passive shielding has been used to reduce the capacitive coupling effects of adjacent bus lines by inserting passive ground or power lines (shields) between them. Active shielding is another shielding technique in which the shield is allowed to switch depending on the switching pattern of its adjacent bus lines. This paper formally derives the optimal active shielding logic function for minimum power dissipation. It is also shown that this optimal active shielding architecture depends on the ratio of coupling to ground capacitance (/spl gamma/=C/sub c//C/sub g/). Optimal active shielding is shown to provide up to 25% reduction in bus power dissipation compared to conventional passive shielding. A suboptimal active shielding architecture with simpler hardware is also proposed. Theoretically, using the suboptimal shielding architecture leads to less than 6% bus power penalty compared to the optimal active shielding logic circuit. However, due to the simpler shield encoding circuitry, simulation results show that the suboptimal active shielding architecture leads to higher overall energy savings compared to the optimal active shielding architectures.

It is shown in this paper that contrary to the common conception, widening an on-chip interconnect wire will not cause the wire to behave as a lossless line. It is shown that the energy losses actually increase when widening a wire. The damping factor of the line, which determines the maximum bit rate that can be transmitted on a wire, also does not go to zero for wide wires as in lossless lines. This fact results in a serious physical limitation on the maximum bit rate that can be transmitted on a wire. It is shown that by increasing the cross-sectional width of an interconnect wire, the damping factor will saturate to a certain limit. An expression for this minimum damping factor for very wide wires is derived from fundamental physical constants and used to introduce an expression for the maximum bit rate that can be reached by widening an interconnect wire for a certain technology. It is shown that for current technology numbers, the maximum bit rate on a wire can be quite limiting for longer wires and that scaling trends will even decrease more this maximum bit rate, posing a serious limitation.

As technology scales, the shrinking wire width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of bus lines of the conventional parallel-line bus CB architecture by multiplexing each m-bits onto a single line. This bus architecture, the serial-link bus SLB, transforms an n-bit conventional parallel-line bus into an n/m-line (serial-link) bus. The advantage of serial-link buses is that they have fewer lines, and if the bus width is kept the same, serial- link buses will have larger line width and spacing. Increasing the line width has a twofold reduction effect on the line resistance, as the resistivity of sub-100 nm wires significantly drops as the line width increases. Also, increasing the line width and spacing reduces the coupling capacitance between adjacent lines, but increases the line-to-ground capacitance. Thus, an optimum degree of multiplexing m exists that minimizes the bus energy dissipation and maximizes the bus throughput per-unit area. The optimum degree of multiplexing for maximum throughput-per- unit-area and for minimum energy dissipation for the 25-130 nm technologies was determined in this paper. HSPICE simulations show that; for the same throughput-per-unit-area as conventional parallel-line buses, the serial-link bus architecture reduces the energy dissipation by up to 31.42% for a 64-bit bus implemented in an intermediate metal layer of a 50 nm technology and a reduction of 52.7% is projected for the 25 nm technology.

This paper proposes a bus architecture called skewed repeater bus (SRB) for reducing on-chip interconnect energy in microprocessors. By introducing relative delay between neighboring bus lines, SRB reduces both average and worst-case coupling capacitance between those lines. SRB is compared to previously published techniques like delayed data bus (DDB) and delayed clock bus (DCB). Simulation results in 65-nm process show that bus energy reduction of 18% is achieved when SRB is applied to a real microprocessor example, versus 11% and 7% only for DDB and DCB; respectively.

It is shown in this paper that the optimum position of interleaved repeaters for minimum delay and noise is not the midpoint as commonly practiced. A closed-form solution for the optimum position has been derived in this paper and verified by simulation. Bidirectional buses with the optimum interleaved repeater position are compared to commonly used bidirectional buses and shown to provide an improvement greater than 50% in the propagation delay and bit-rate per unit area. The area of the induced noise pulse on victim lines is shown to be zero indicating that the aggressor lines are virtually static with the optimum repeater position. The presented optimum repeater positioning also provides lower noise pulse amplitude as well as lower sensitivity of propagation delay and noise pulse peak to segment length variation, compared to commonly used midway repeater positioning.

Passive shielding has been used to reduce capacitive coupling effects of adjacent bus lines by inserting passive ground or power lines (shields) between the bus lines. Active shielding is another shielding technique, in which the shield is allowed to switch depending on the switching pattern of its adjacent bus lines. This work formally derives the optimal active shielding logic function for minimum power dissipation. It is also shown that this optimal active shielding architecture depends on the ratio of coupling to ground capacitance (/spl gamma/ = C/sub c//C/sub g/). Optimal active shielding is shown to provide up to 25% reduction in bus power dissipation compared to conventional passive shielding. A sub-optimal active shielding architecture with simpler hardware is also proposed. Simulation results show that using the sub-optimal shielding architecture leads to less than 6% bus power penalty compared to the optimal active shielding logic circuit.

This paper presents a comprehensive qualitative and analytical analysis of the effect of relative delay on the dissipated energy of coupled lines. Closed form expressions modeling the effect of relative delay on the dissipated energy, and the Miller coupling factor, MCF, are also presented. Skewing the worst switching case is shown to provide up to 50% reduction in energy dissipation. This observation was implemented in a low-power bus scheme, DLBS, which leads to a power reduction of up to 25%.

This paper presents an analysis of how the power dissipation of on-chip buses is affected by introducing a relative delay between the switching lines. Relative delay is shown to reduce the dissipated power of oppositely switching lines while causing a power penalty for similarly switching lines. A new low-power bus scheme that uses this effect is proposed and analyzed. As the introduced delay increases, the achieved power reduction increases while decreasing the bus throughput. Thus, a tradeoff between power reduction and throughput is required when selecting the imposed relative delay. The proposed low-power scheme, dynamic delayed line bus (DDL) scheme, led to a power reduction of up to 25%, 33%, and 42% when applied to data, address, and differential buses, respectively. Simple DDL hardware is designed and implemented in a 0.18-/spl mu/m TSMC CMOS technology and applied to a 4500-/spl mu/m long Metal4 bus. Circuit simulation results for different bus widths are presented.

It is shown in this paper that the optimum position of interleaved repeaters for minimum delay and noise is not the midpoint as commonly practiced. A closed form solution for the optimum position has been derived in this paper and verified by simulation. Bi-directional buses with the optimum interleaved repeater position are compared to commonly used bi-directional buses and shown to provide an improvement of as much as 100% in both the propagation delay and bit-rate per unit area. The area of the induced noise pulse on victim lines is shown to be zero indicating that the aggressor lines are virtually static when optimum repeater positioning is used.