Integrated circuit (IC) identification using unclonable digital fingerprints facilitates the authentication of ICs, device tracking, and cryptographic functions. In this paper, we present two hardware methods exploiting the inherent process-induced mismatch of SRAM cells. The proposed circuits improve upon those previously published by reducing the number of bits that vary from trial to trial, and can be used at times other than just IC power-up. The proposed circuits and methods are compared with the previous power-up approach using the experimental results from a 90-nm test chip. The required SRAM array periphery circuit changes allow the use of standard foundry SRAM cells and do not impact the memory access time.

Hardening the flip-flops and latches is the most straightforward way to improve the soft-error robustness of sequential logic circuits. This paper presents novel pulse-clocked latch based flip-flops that mitigate not just single event upsets (SEUs) but also single event transients (SETs) that are an increasing threat in high performance logic. The design uses triple-mode redundant latches, combined with appropriate clocking to provide redundancy in both space and time. Analysis of the flip-flop operation and immunity to both SEUs and SETs, as well as layout that provides adequate critical node separation to prevent multi-node charge collection failures, are presented. The multi-bit flip-flop macro has been fabricated and tested functional as shift registers on a 90-nm foundry LP process.

Measurement and extraction of as fabricated SRAM cell variability is essential to process improvement and robust design. This is challenging in practice, due to the complexity in the test procedure and requisite numerical analysis. This work proposes a new singleended test procedure for SRAM cell write margin measurement. Moreover, an efficient decomposition method is developed to extract transistor threshold voltage (VTH) variations from the measurements, allowing accurate determination of SRAM cell stability. The entire approach is demonstrated in a 90nm test chip with 32K cells. The advantages of the proposed method include: (1) a single-ended SRAM test structure with no disturbance to SRAM operations; (2) a convenient test procedure that only requires quasistatic control of external voltages; and (3) a non-iterative method that extracts the VTH variation of each transistor from eight measurements. The new procedure enables accurate predictions of SRAM performance variability. As validated with 90nm data of write margin and data retention voltage, the prediction error from extracted VTH variations is < 4% at all corners.