A novel and efficient method is presented for computing the delay and supply current pulse in a CMOS inverter with an RC load. The method builds on existing techniques for computing these quantities in the presence of a capacitance load. As in the work of other authors, the concept of an effective capacitance C/sub eff/ is used. However, here it captures the inverter's behavior only while the charging/discharging transistor is in saturation and, therefore, behaves like a current source to a good approximation. This capacitance is determined by means of a simple iterative procedure that uses an empirical piecewise-linear approximation to the RC circuit's output voltage, which has a normal CMOS symmetrical form. Since a C/sub eff/ defined in the above way is independent of the inverter's parameters, such as transistor size, the coefficients of the approximation have to be determined for only one reference inverter. A simple analytical method yields the inverter's output voltage outside the saturation region. The complete model has been shown to be accurate for both 0.8-/spl mu/m 5-V and 0.24-/spl mu/m 2.5-V CMOS technologies. Its speed is comparable to that of the "capacitance load" techniques that it relies on.

This paper presents techniques for reducing CMOS gates to equivalent inverters for current and delay analysis. These do not assume a single input switching, and they account for the speed of the input transitions, as well as for the relative positions of the inputs in series-connected MOSFETs. The resulting inverters have been tested using previously published current analysis techniques. The gate reduction time is small compared to that for determining the current, and there is no significant effect on the accuracy.>

The subject of this paper is the reduction of transistor-level models of CMOS logic gates to equivalent inverters, for the purpose of computing the supply current in digital circuits. No restrictions are applied to either the number of switching inputs or the transition times and relative delays of the input voltages. The relative positions of the switching inputs are also accounted for in the case of series-connected MOSFET's. When combined with our previously reported CMOS inverter model, the peak current is obtained in a time approximately three orders faster than HSPICE with the level-3 MOSFET model. The corresponding accuracy is around 12%. If the current waveform is required, the speed improvement is about an order less. Since the inverter model also yields the delay at no extra cost, the timing of the current waveforms can be done automatically, without recourse to a timing simulator. Although the emphasis here is on CMOS static gates, the method is applicable to dynamic logic gates as well.>

Most existing techniques for computing the delay in linear resistance-capacitance (RC) networks will yield inaccurate results when applied to MOS transistor circuits, because they do not provide a means for determining the MOSFET's effective channel resistance, which is a function of the capacitive load. The iterative method, in which the RC network is converted to a tree by node splitting is an exception. An efficient algorithm which takes the above dependence into account by adjusting the resistances in the model within the iterative process of the LM algorithm is presented. It is shown that by focusing on high-capacitance nodes and by distributing the split capacitances on the basis of path conductances, it is possible in many cases to dispense with iteration. For large transistor groups, decomposition into biconnected components is shown to be very effective. Combinations of these techniques have been tested on a large variety of circuits, a representative subset of which is presented.>

An accurate and fast analytical technique for computing the delay and the maximum supply current in a CMOS inverter is presented. It accounts for the effects of input slope, output load, transistor size, and short-circuit current. The accuracy is within 10% of the HSPICE level-3 model and the speed is more than three orders of magnitude faster than HSPICE. An extension of this technique is shown for the calculation of the delay and the maximum supply current of a chain of inverters, without recourse to integration. An efficient method for computing the total current waveform of the chain is also presented. The relative speed of computing the current waveform exceeds two orders of magnitude compared to HSPICE.>

The relationship between switch-level circuit models and the linear electric circuits from which they are abstracted is investigated. This is important in determining the accuracy and consistency of switch-level simulation programs. A precise definition of magnitude or strength classes is presented, which leads to exact bounds on the accuracy of resistance and voltage calculations with magnitude classes relative to the corresponding linear calculations. The results indicate that the potential of switch-level simulators to provide accurate results is far less than was previously thought.>

The authors present three algorithms for efficient worst-case delay estimation in transistor groups using transistor-level delay models and timing simulation techniques. The first algorithm, dynamic path selection (DPS), determines the path with the longest delay in a transistor group. If the group consists of series-parallel transistor combinations, the time complexity is linear. The second algorithm, delay subnetwork enumeration (DSE), complements the DPS method by taking into account logic dependencies. The paths with the shortest delay are computed using the dynamic cut selection (DCS) algorithm. These techniques have been implemented in the static timing analyzer TAMIA to provide fast and accurate worst-case delay estimation for digital CMOS circuits.>

An efficient recursive technique for computing the Elmore delay in series-parallel resistance-capacitance (RC) networks is presented. The time complexity of the algorithm is on the order of the number of resistors times the number of nodes to which the delay has to be computed. In this respect it is superior to other known methods, particularly to that of P.K. Chan Karplus. Although that algorithm is more general, the present method should be attractive given the fact that many VLSI MOS circuits are based on design styles which are restricted to series-parallel transistor networks, which, in particular, exclude bridges. A special type of series-parallel RC circuit occurs in interconnection networks driven by multiple sources. A variation on the first algorithm, which is especially useful in a hierarchical simulator, is presented for computing the Elmore delay in such networks.>

This paper presents two algorithms for performing worst-case delay estimation using transistor-level timing simulation techniques. The first algorithm, Dynamic Path Selection (DPS), determines in linear time the slowest paths in series-parallel transistor groups; the exponential complexity remains for transistor groups with bridges. The second algorithm, Delay Subnetwork Enumeration (DSE), complements the DPS method by taking into account logic dependencies within transistor groups. The two methods are combined in the static timing analyzer TAMIA, to provide accurate worst-case delay estimation of digital CMOS circuits.

The relationship between switch-level circuit models and the linear electric circuits from which they are abstracted were investigated. This is important in determining the accuracy and consistency of switch-level simulation programs. A precise new definition of magnitude or strength classes is presented, which leads to exact bounds on the accuracy of resistance and voltage calculations with magnitude classes relative to the corresponding linear calculations. The applicability to switch-level networks of standard solution methods for linear networks, including Gaussian elimination and Jacobi iteration, is also examined. The results indicate that the potential of switch-level simulators to provide accurate results is far less than previously thought.>

An algorithm has been developed for the automatic determination of the optimal clock waveforms for synchronous circuits containing level-sensitive latches. From a specification of only the number of clock phases, the rise and fall times of the clock phase transitions, and the order in which they occur, the algorithm computes the minimum time interval between the transitions, while accounting for the clock skew. Timing errors, such as incorrect hold times, are also detected. Existing procedures, in contrast, either verify if a circuit meets a given specification of these clock intervals, or they work with a very restricted set of clocking schemes. The procedure is iterative, and can be formulated as a linear programming problem. It yields an upper bound on the shortest valid clock period at each iteration. Results are presented for a simplified form of this algorithm, implemented in the transistor-level timing analysis program TAMIA.>

Various algorithmic and heuristic techniques are proposed for dealing with the problem of computing delays in switch-level models of MOS transistor circuits which contain loops. The nonlinear dependence of the effective channel resistance on the capacitive load is dealt with by adjusting the resistance within the iterative process of computing delay, using the Lin and Mead algorithm. Heuristics are proposed for reducing the number of iterations by splitting the loops at high capacitance nodes and by basing the initial values of the split capacitances on the path conductances. It is demonstrated that the decomposition of the transistor groups into bicomponents is very effective for large groups. Combinations of these techniques have been tested on a large variety of circuits, a representative subset of which is presented.>

Soft errors caused by ionizing radiation will be a limiting factor in the reliability of VLSI circuits with submicron-feature sizes. A new approach to the design of soft-error-tolerant digital integrated circuits'is presented. It is based on the filtering of transients at register inputs, and it incurs a lower area overhead than known techniques. The method, called soft-error filtering (SEF), is derived on the basis of the analogy between a noise-sensitive finite-state machine and a noisy communication channel. The necessary characteristics of the register are examined and a design is presented for the associated filter. It is shown that SEF can be used to reduce the associated error rate to insignificant levels.

As the semiconductor industry continues to scale down the feature sizes in VLSI digital circuits, soft errors will eventually limit the reliability of these circuits. An important source of these errors will be the products of radioactive decay. It is proposed to combat these transient errors by a new technique called soft-error filtering (SEF). This is based on filtering the input to every latch in the VLSI circuit, thereby preventing these transients, generated by alpha particle hits in the combinational section, from being latched in the corresponding registers. Several approaches to the problem of designing filtering latches are compared. This comparison demonstrates the superiority of a double-filter realization. The design for a CMOS implementation of the double-filter latch is presented. Not only is the design simple and efficient, but it can be expected to be tolerant to process variations. A comparison of SEF with conventional techniques for dealing with soft errors shows the former to be generally much more attractive, from the point of view of both area and time overhead.

A new logic minimization algorithm is presented. It finds a minimal cover for a multiple-output boolean function expressed as a list of cubes. A directed graph is used to speed up the selection of a minimal cover. Covering cycles are partitioned and branched independently to reduce greatly the branching depth. The resulting minimized list of cubes is guaranteed to be minimal in the sense that no cover with less cubes can exist. The don't care at output is handled properly. This algorithm was implemented in C language under UNIX BSD4.2. An extensive comparison with ESPRESSO IIC shows that the new algorithm is particularly attractive for functions with less than 20 input and 20 output variables.

A new logic minimization algorithm is presented. It finds a minimal cover for a multiple-output Boolean function expressed as a list of cubes. A directed graph is used to speed up the selection of a minimal cover. Covering cycles are partitioned and branched independently to reduce greatly the branching depth. The resulting minimized list of cubes is guaranteed to be minimal in the sense that no cover with less cubes can exist. The dont care at output is handled properly. This algorithm was implemented in C under UNIX BSD4.2. An extensive comparison with ESPRESSO IIC shows that the new algorithm is particularly attractive for functions with less than 20 input and 20 output variables.