Densification of network with numerous small cells is an important aspect of 5G radio access network (RAN). Planning of backhaul connectivity for these small cells has become crucial for cost effective deployment of the network. Integrated access and backhaul (IAB) node has been envisaged to address this important aspect. In this work, we have considered a scenario where, an existing telecom service provider (TSP) plans to augment its network by deploying additional multiple small base stations (SBSs) at different locations. We consider that the TSP has optical fiber cable (OFC) at few existing locations. Hence, the SBS may be integrated by laying of OFC from nearest OFC available location. Alternatively, self-backhauled SBSs may be employed for the integration. In case of OFC backhaul, involvement of capital expenditure (CAPEX) will be higher. On the other hand, the deployment of self-backhauled SBSs causes higher interference to the users in the network. Hence, optimal deployment policy for the TSPs is required considering usage patterns of the subscribers, CAPEX involvement, deployment hindrance, and resulting interference in the network. The problem of cost effective deployment of the 5G RAN has been posed as an optimization problem. Subsequently, novel GA based hybrid backhauling (GAHB) technique has been presented. Our simulation results show that GAHB outperforms All Wired (AW) and All Unwired (AU) approaches as far as total cost of ownership (TCO) of the network is concerned.

In this paper, we study two different ON-chip power delivery schemes, namely, fully integrated voltage regulator (FIVR) and low-dropout regulator (LDO), and analyze their effect on total system power under process variation, assuming a realistic dynamic voltage-frequency scaling (DVFS) system. The impact of different task scheduling algorithms on the overall system power was also analyzed. We find that in a hypothetical 256-core processor, under a per-core DVFS assumption, the FIVR-based power delivery consumes 20% less power than the LDO-based one for a 50% throughput. However, as the number of cores in the processor reduces, the difference in power consumption between the FIVR-based and LDO-based power delivery schemes becomes smaller. For example, in the case of a 16-core processor with per-core DVFS capability, FIVR-based design was found to consume about the same power as the LDO-based design.

As the end draws near for Moore's law, the search for low-power alternatives to complementary metal-oxide-semiconductor (CMOS) technology is intensifying. Among the various post-CMOS candidates, spintronic devices have gained special attention for their potential to overcome the power and performance limitations of CMOS. In particular, all spin logic (ASL) technology, which performs Boolean operations and transfers the output in the spin domain, has been proposed for enabling new capabilities-such as high density, low device count, and nonvolatility-that were previously impossible with CMOS technology. In this paper, first we provide an overview of the history and the current status of the various spintronic devices being pursued by the research community. Then, we describe how spin-based components are integrated into a computing system and the advantages that result. We use a hypothetical spintronic-based Intel Core i7 as a test vehicle to compare the system-level power requirements of ASL- and CMOS-based systems, taking into consideration the unique demands of spin-based interconnects. We conclude with a brief analysis of current limitations and future directions of spintronic research.

Dynamic voltage and frequency scaling (DVFS) is a powerful technique to reduce power consumption in a chip multiprocessor. To support DVFS in the multicore power delivery network, we integrate on-chip switched-capacitor (SC) dc-dc converters that can work with multiple conversion ratios to provide varying levels of Vdd supplies. We study the application of such SC converters in multicore chips by simulation. Our results show that distributed SC converters can significantly reduce the voltage droop seen by the local core loads by providing better localized power regulation. Considering the fact that the current distribution in a multicore chip is unbalanced, we further develop computer-aided design techniques to automate the design (size) and distribution (number and location) of these SC converters, using the efficiency of the whole power delivery system as the optimization metric. This is a major concern, but has not been addressed at the system level in prior research. We develop models for the power loss of such a system as a function of size and distribution of the SC converters, then propose an approach to optimize the SC converters to maximize the efficiency of the system, while considering all the possible conversion ratios an SC converter can work with. We verify the accuracy of our models for the power loss in the power delivery system, and demonstrate the efficiency of our techniques to optimize the SC converters on both homogenous and heterogenous multicore chips.