This article presents a new approach to automate the setup of the design equations of the manual analog design process. Its main contribution is a comprehensive hierarchical performance equation library (HPEL) for op-amps. The HPEL makes the setup of design equations independent of the topology. Based on the library and the functional block recognition method in Abelet al.(2020), analytical performance models for various op-amp topologies are automatically instantiated. The method is currently designed for basic op-amps. In this article, we use the method to size different op-amp topologies. Experimental results featuring four circuits are presented. The HPEL has also been integrated into a structural synthesis method featuring several thousand op-amp topologies (Abel and Graeb, 2021).

Extracting structural information of a design is one crucial aspect of many circuit verification and synthesis methods. State-of-the-art structure recognition methods use a predefined building block library to identify the basic building blocks in a circuit. However, the capability of these algorithms is limited by the scope, correctness and completeness of the provided library. This paper presents a new method to automatically generate the recognition rules required to identify a given circuit topology in a large design. Device pairs are grouped into building blocks by analyzing their characteristics, e.g., their connectivity, to enable a structure recognition as unambiguous as possible. The resulting blocks are consecutively assembled to larger blocks until the full building block description of the given topology has been established. Building block libraries dedicated to one specific topology type, e.g., operational amplifiers, can be obtained by applying the method to its basic version, subsequently extending the generated library by the additional elements required to identify its topology variants using the presented method. Experimental results for six folded cascode amplifier and five level shifter topologies are given.

This paper presents a new method to automate the initial sizing of operational amplifiers. The method emulates the manual design procedure. The sizing task is formulated as a constraint programming problem. Two new algorithms are introduced: First, a hierarchical structural analysis of functional blocks that automatically sets up the analytical equations for the sizing. And second, a heuristic to guide branching process of a constraint programming solver. We achieve a reproduction of the manual proceeding of designers and at the same time an automation of the set-up of the design problem, reducing the set-up effort from months to seconds. 16 topologies, including different variants of two-stage, folded-cascode, telescopic and symmetrical op-amps, are considered at this time. In this paper, experimental results for a two-stage op-amp and a folded-cascode op-amp are presented to show the effectiveness of the approach.

Modern system-on-chip designs implement sophisticated power management features to achieve better energy efficiency. This includes power-down modes for analog circuit blocks. Typically, they are implemented by additional power-down circuitry which shuts down all bias currents. During the design of power-down circuitry, it must be ensured that the circuit still meets all specifications in normal operation. Furthermore, floating nodes and asymmetric stress need to be avoided in order to reduce device degradation over time. Therefore, the manual design of power-down circuitry can become a challenging and time consuming task requiring alternating implementation and verification phases. In this paper, a power-down synthesis methodology is presented which constructs fault-free power-down circuitry by systematically applying typical shutoff patterns. Furthermore, the synthesized power-down circuitry is visualized in the circuit schematic to support the designer in capturing the structure of the inserted power-down circuitry. Finally, the sizing of power-down transistors is determined automatically. Experimental results for three amplifier circuits, a voltage controlled ring oscillator and a low voltage differential signaling driver demonstrate the efficiency and efficacy of the presented methods.