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I-Ting Wang

dblp:170/0117 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2016
0000-0002-4626-4592ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
non-volatile memory
0.212016
3D resistive RAM cell design for high-density storage class memory - a review · Sci. China Inf. Sci. 2016
Memory systems › non-volatile memory
resistive memory
0.212016
3D resistive RAM cell design for high-density storage class memory - a review · Sci. China Inf. Sci. 2016
Memory systems › non-volatile memory
storage class memory
0.112016
3D resistive RAM cell design for high-density storage class memory - a review · Sci. China Inf. Sci. 2016

Methods — techniques the papers use, named apart from their topics

review · 0.2
YearPublicationVenuePosition
2016 3D resistive RAM cell design for high-density storage class memory - a review
Boris Hudec, Chung-Wei Hsu, I-Ting Wang, Wei-Li Lai, Che-Chia Chang, Taifang Wang, Karol Fröhlich, Chia-Hua Ho, Chen-Hsi Lin, Tuo-Hung Hou
Sci. China Inf. Sci.3
2015 Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning
abstract
The cross-point array architecture with resistive synaptic devices has been proposed for on-chip implementation of weighted sum and weight update in the training process of learning algorithms. However, the non-ideal properties of the synaptic devices available today, such as the nonlinearity in weight update, limited ON/OFF range and device variations, can potentially hamper the learning accuracy. This paper focuses on the impact of these realistic properties on the learning accuracy and proposes the mitigation strategies. Unsupervised sparse coding is selected as a case study algorithm. With the calibration of the realistic synaptic behavior from the measured experimental data, our study shows that the recognition accuracy of MNIST handwriting digits degrades from ∜97 % to ∜65 %. To mitigate this accuracy loss, the proposed strategies include 1) the smart programming schemes for achieving linear weight update; 2) a dummy column to eliminate the off-state current; 3) the use of multiple cells for each weight element to alleviate the impact of device variations. With the improved synaptic behavior by these strategies, the accuracy increases back to ∜95 %, enabling the reliable integration of realistic synaptic devices in the neuromorphic systems.
Pai-Yu Chen, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao 0001, Shimeng Yu
ICCAD3