Traditional statistical static timing analysis (SSTA) using available single-input switching (SIS) based gate delay libraries either ignore timing impact from multiple-input switching (MIS) or use single-corner (deterministic) models for MIS consideration. This paper presents a method for modeling the impact of MIS on statistical timing accurately using concepts of convolution and chain ruling. Experimental results in a commercial SSTA framework demonstrate negligible run-time overheads of modeling MIS while accurately exposing timing slack optimism in an SIS based flow of up to 17 pico-seconds on designs mapped to a 14 nanometer technology library. Prediction of timing critical paths due to MIS show excellent correlation to silicon hardware. Comparisons with prior work illustrate the accuracy improvements of the presented work.

We describe a timing analysis engine for efficient processing of incremental changes to a circuit. The engine uses a block-based approach for incremental slack propagation. Logic cones affected by incremental changes to the design are identified and used to restrict the scope of the computation. Incremental block-based clock-pessimism removal and reporting of worst paths in the circuit is implemented using a novel dynamic path reduction technique. The engine is very efficient in memory usage compared to other known academic timers while maintaining a very high accuracy of reported path slacks when compared to a standard industrial timing engine. Certain paths are intentionally omitted from reporting in order to save on runtime, while ensuring that all paths with highest criticality are covered. Our timer (iitRACE) placed overall third in TAU 2015 contest on incremental timing analysis. Experimental results on industrial benchmarks from TAU 2015 contest have justified that iitRACE has average memory requirement 2X and 30X lower than that of first and second place timers respectively.