This work presents a ring oscillator (RO)-based low-jitter injection-locked clock and data recovery (ILCDR) with a pattern-dependent pulse filtering (PDPF) technique. The conventional ILCDR has a drawback that data jitter is transferred to the recovered clock. To reduce jitter, the PDPF technique is employed to filter out the injection pulses occurring in data patterns that cause high data-dependent jitter (DDJ). Adopting the PDPF technique with an injection timing control loop, the ILCDR optimizes injection timing and maximizes timing margin. Fabricated in a 28-nm CMOS technology, the proposed ILCDR occupies an active area of 0.03 mm2and consumes 13.6 mW at 10 Gb/s. The measured jitter tolerance (JTOL) is 1 UIppat 35 MHz with a bit error rate (BER) of$10^{-12}$.

This brief proposes a digital phase-locked loop (DPLL) with a power supply noise (PSN) regulated ring-type digitally controlled oscillator (DCO) using an nMOS shunt regulator array. The proposed nMOS array dynamically detects the PSN and creates a pathway, channeling the PSN forwarded through the digitally controlled resistor (DCR) directly to the ground. To support the proposed power supply noise compensation (PNC) technique in wide-range operation, the output bits from the digital loop filter (DLF) control not only the DCR but also the total transconductance of the nMOS array. The supply-sensing amplifier (SSA) between the supply and the gates of the nMOS array amplifies supply noise to lower the voltage headroom, allowing the DCO to run faster. Fabricated in 40-nm CMOS technology, the prototype DPLL demonstrates an rms jitter of 1.27 ps under 1 MHz, 20-mVPPsinusoidal noise, while the rms jitter without the regulator is measured as 3.26 ps. The total power consumption and area occupation of the DPLL are 13.5 mW and 0.066 mm2, respectively. The proposed scheme for PNC contributes only 1.90 mW and 0.0017 mm2, representing 14.1% and 2.8% of the total, respectively.

This article presents a design methodology for compact single-channel 1 GS/s 8-bit 3-stage capacitor-array-assisted charge-injection DAC-based SAR ADC. A detailed framework of an information rate density (IRD) is mainly investigated in this work. With the proposed framework, an 8-bit prototype ADC reaches the highest IRD thanks to the optimum choice of DAC construction. To improve the performance of the ADC, we propose various circuit techniques such as 1) DC dependence compensation of charge-injection cell (ci-cell), 2) up-then-down DAC switching sequence, and 3) metastability detection to prevent the sparkle code error. The prototype ADC was fabricated in a 28-nm CMOS process and occupies an ultra-compact active area of 0.000261 mm2, the smallest among the previously reported designs. At a 1.0 V supply voltage and 1 GS/s operation, the proposed ADC achieves an SNDR of 43.5 dB and dissipates 2.61 mW at the Nyquist rate, resulting in the state-of-the-art IRD of 470 TS/s$\cdot $conv/mm2.

In this paper, the amount of phase shift with result of the pulse injection is derived mathematically and verified by simulation. The resultant phase shift is proportional to injection pulse width, and inversely proportional to on-resistance of the switch and total capacitance parallel to injection transistor. In addition, phase shift has sinusoidal form with two times the oscillation frequency. Furthermore, locking range can be estimated using the amount of the maximum resultant phase shift. Thereby, it is verified that pulse injection-locked oscillators using shorting scheme have two locking points in one period.