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Hyunseung Han

dblp:170/6479 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware reliability and fault tolerance · 72% Memory systems · 18% Integrated circuit design · 5%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance › error correction
error-correcting codes
0.622018
READ: Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution · IEEE Trans. Computers 2018
Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Hardware reliability and fault tolerance
soft errors
0.422018
READ: Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution · IEEE Trans. Computers 2018
Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Memory systems
3d-stacked memory
0.312018
READ: Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution · IEEE Trans. Computers 2018
Hardware reliability and fault tolerance
memory reliability
0.312017
Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Integrated circuit design
3d integration
0.112018
READ: Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution · IEEE Trans. Computers 2018
Electronic design automation › hardware test
memory built-in self-repair
0.112017
Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017

Methods — techniques the papers use, named apart from their topics

redundancy sharing · 0.3heterogeneous ECC organization · 0.3spare column utilization · 0.3defect information storage · 0.3content-addressable memory · 0.3
YearPublicationVenuePosition
2018 READ: Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution
abstract
3D-memory is one of promising applications in 3D-IC technology. With a 3D integration technology, the effective density of memories can increase and the interconnect distance from processor to memory can be shortened. Due to its stacked structure, the upper dies behave as shields blocking outer particles from reaching lower dies, and it makes error rate of the top layer largest among all layers. From a heat perspective, the lower dies would suffer from reliability problems since the lower dies are placed on top of logic die. The heat dissipation can more influence lower dies than upper dies. This creates unequal a reliability distribution for each layer in 3D-memories. A novel ECC organization scheme for 3D-memory to secure reliable operations under soft error rate (SER) profiles is introduced in this paper. The proposed scheme does not require additional redundant arrays. Instead, it utilizes unused spare columns of relatively reliable layer memories to store additional check-bits of less reliable layer memories. It forms a heterogeneous ECC organization across different layers which enhances ECC capabilities in less reliable layers. In addition, redundancy sharing scheme for yield enhancement can be implemented with the proposed scheme. Experimental results show that a memory with the proposed method can tolerate more than three times of a bit-error rate compared to the conventional memory.
Hyunseung Han, Jaeyong Chung, Joon-Sung Yang
IEEE Trans. Computers1
2017 Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC
abstract
Due to the emergence of extremely high density memory along with the growing number of embedded memories, memory yield is an important issue. Memory self-repair using redundancies to increase the yield of memories is widely used. Because high density memories are vulnerable to soft errors, memory error correction code (ECC) plays an important role in memory design. In this paper, methods to exploit spare columns including replaced defective columns are proposed to improve memory ECC. To utilize replaced defective columns, the defect information needs to be stored. Two approaches to store defect information are proposed-one is to use a spare column and the other is to use a content-addressable-memory. Experimental results show that the proposed method can significantly enhance the ECC performance.
Hyunseung Han, Nur A. Touba, Joon-Sung Yang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1