This paper explores CMOS-compatible Ferroelectric Tunnel Junctions (FTJs) for Processing-In-Memory (PIM) to address the ‘memory wall’ in traditional computing. A novel FTJ noise model was developed, and hardware-calibrated devices were modeled utilizing IBM's Analog In-Memory Hardware Acceleration Toolkit (AIHWKit). We simulate FTJ-based neural networks for inference only, focusing on mitigating non-idealities such as conductance drift, programming noise, and 1/f read noise. To mitigate FTJ non-idealities affecting different neural networks' accuracy, we developed various hardware-aware (HWA) training techniques including, but not limited to, different weight redistribution, noise resiliency, and custom activation functions. Exploiting the hardware-aware techniques used in this paper, considering different weight-to-conductance mapping and conductance and weight range enlargement, depicts an accuracy improvement in three case studies: full adder implementation, MNIST and CIFAR-10 benchmark, with best-case scenario accuracy of 96.96 %, 86.92 %, and 86.36 %, respectively, after four months of inference. Furthermore, scalability, accuracy im-provement, and experimental validation confirm FTJs' potential for Processing-in-Memory, providing valuable insights for future device and circuit design optimizations to enhance performance and reliability.

Novel non-volatile memory devices based on ferroelectric thin films represent a promising emerging technology that is ideally suited for neuromorphic applications. The physical switching mechanism in such films is the nucleation and growth of ferroelectric domains. Since this has a strong dependence on both pulse width and voltage amplitude, it is important to use precise pulsing schemes for a thorough characterization of their behavior. In this work, we present an on-chip 120 dB programmable range pulse generator, that can generate pulse widths ranging from 10 ns to 10 ms ± 2.5% which eliminates the RLC bottleneck in the device characterisation setup. We describe the pulse generator design and show how the pulse width can be tuned with high accuracy, using Digital to Analog converters. Finally, we present experimental results measured from the circuit, fabricated using a standard 180 nm CMOS technology.

Ferroelectric tunneling junctions (FTJ) are considered to be the intrinsically most energy efficient memristors. In this work, specific electrical features of ferroelectric hafnium-zirconium oxide based FTJ devices are investigated. Moreover, the impact on the design of FTJ-based circuits for edge computing applications is discussed by means of two example circuits.