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Fahui Jia

dblp:171/1007 · DBLP profile ↗
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2ranked-venue papers
1as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 33% Reconfigurable computing and FPGAs · 33% Processor architecture and microarchitecture · 33%
Databases, data mining, and information retrieval
1 paper
Data mining · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › machine learning accelerator
clustering accelerator
0.512021
An FPGA Based Accelerator for Clustering Algorithms With Custom Instructions · IEEE Trans. Computers 2021
Processor architecture and microarchitecture › instruction set architecture › instruction set customization
custom instruction set
0.512021
An FPGA Based Accelerator for Clustering Algorithms With Custom Instructions · IEEE Trans. Computers 2021
Reconfigurable computing and FPGAs
FPGA accelerator
0.512021
An FPGA Based Accelerator for Clustering Algorithms With Custom Instructions · IEEE Trans. Computers 2021
Data mining
clustering
0.112021
An FPGA Based Accelerator for Clustering Algorithms With Custom Instructions · IEEE Trans. Computers 2021
Data mining › clustering
k-means clustering
0.112021
An FPGA Based Accelerator for Clustering Algorithms With Custom Instructions · IEEE Trans. Computers 2021

Methods — techniques the papers use, named apart from their topics

manhattan distance · 1.0euclidean distance · 1.0custom instruction set · 1.0
YearPublicationVenuePosition
2021 An FPGA Based Accelerator for Clustering Algorithms With Custom Instructions
abstract
Clustering algorithms are becoming popular and widely applied in many academic fields, such as machine learning, pattern recognition, and artificial intelligence. It has posed significant challenges to accelerate the algorithms due to the explosive data scale and wide variety of applications. However, previous studies mainly focus on the raw speedup with insufficient attention to the flexibility of the accelerator to support various applications. In order to accelerate different clustering algorithms in one accelerator, in this article, we design an accelerating framework based on FPGA for four state-of-the-art clustering methods, including K-means, PAM, SLINK, and DBSCAN algorithms. Moreover, we provide both euclidean and Manhattan distances as similarity metrics in the accelerator design paradigm. Moreover, we provide a custom instruction set to operate the accelerators within each application. In order to evaluate the performance and hardware cost of the accelerator, we constructed a hardware prototype on the state-of-the-art Xilinx FPGA platform. Experimental results demonstrate that the accelerator framework is able to achieve up to 23× speedup than Intel Xeon processor, and is 9.46× more energy efficient than NVIDIA GTX 750 GPU accelerators.
Chao Wang 0003, Lei Gong 0003, Fahui Jia, Xuehai Zhou
IEEE Trans. Computers3
2015 SAKMA: Specialized FPGA-Based Accelerator Architecture for Data-Intensive K-Means Algorithms
Fahui Jia, Chao Wang 0003, Xi Li 0003, Xuehai Zhou
ICA3PP (2)1