Zhisheng Huo

dblp:171/1089 · DBLP profile ↗
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22ranked-venue papers
4as first author
11since 2021 · last 2026
0000-0002-5366-0892ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 11 · 4 first-author · 3 since 2021Applied, interdisciplinary, general and emerging computing · 8 · 5 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021Computer networks · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021Databases, data management, data science and information retrieval · 1 · 1 since 2021Human-computer interaction and ubiquitous computing · 1 · 1 since 2021
YearPublicationVenuePosition
2026 A two-stage data placement strategy for cloud-edge-device collaborative environment
Runnan Shen, Jinquan Wang, Zhisheng Huo, Limin Xiao 0001, Shengyang Tan, Yuntong Li, Xiangrong Xu 0002, Liang Wang 0020
Comput. Commun.3
2026 MEIS: Optimizing deduplication system with efficient index structure
Runnan Shen, Jinquan Wang, Zhisheng Huo, Limin Xiao 0001, Jiantong Huo, Minyi Guo, Jing Shang 0001
J. Syst. Archit.3
2025 CoServe: Efficient Collaboration-of-Experts (CoE) Model Inference with Limited Memory
abstract
Large language models like GPT-4 are resource-intensive, but recent advancements suggest that smaller, specialized experts can outperform the monolithic models on specific tasks. The Collaboration-of-Experts (CoE) approach integrates multiple expert models, improving the accuracy of generated results and offering great potential for precision-critical applications, such as automatic circuit board quality inspection. However, deploying CoE serving systems presents challenges to memory capacity due to the large number of experts required, which can lead to significant performance overhead from frequent expert switching across different memory and storage tiers.
Jiashun Suo, Xiaojian Liao, Limin Xiao 0001, Jinquan Wang, Xiao Su 0002, Zhisheng Huo
ASPLOS (2)7
2025 An adaptive dung beetle optimizer based on an elastic annealing mechanism and its application to numerical problems and optimization of Reed-Muller logic circuits
abstract
The dung beetle optimizer (DBO) is a metaheuristic algorithm with fast convergence and powerful search capabilities, which has shown excellent performance in solving various optimization problems. However, it suffers from the problems of easily falling into local optimal solutions and poor convergence accuracy when dealing with large-scale complex optimization problems. Therefore, we propose an adaptive DBO (ADBO) based on an elastic annealing mechanism to address these issues. First, the convergence factor is adjusted in a nonlinear decreasing manner to balance the requirements of global exploration and local exploitation, thus improving the convergence speed and search quality. Second, a greedy difference optimization strategy is introduced to increase population diversity, improve the global search capability, and avoid premature convergence. Finally, the elastic annealing mechanism is used to perturb the randomly selected individuals, helping the algorithm escape local optima and thereby improve solution quality and algorithm stability. The experimental results on the CEC 2017 and CEC 2022 benchmark function sets and MCNC benchmark circuits verify the effectiveness, superiority, and universality of ADBO.
Lixin Miao, Zhenxue He, Xiaojun Zhao, Kui Yu, Limin Xiao 0002, Zhisheng Huo
Frontiers Inf. Technol. Electron. Eng.8
2025 Hierarchical Hashing: A Dynamic Hashing Method With Low Write Amplification and High Performance for Non-Volatile Memory
abstract
The hashing method is widely used as the index structure, which can be stored in NVM to improve the application performance. However, existing hashing methods may cause high extra write amplification to NVM and bring high additional storage overhead on NVM while providing low request performance. To solve these problems, we have proposed a dynamic hashing method calledHierarchical Hashing, whose basic idea is to leverage a novel hash collision resolution mechanism that can dynamically expand the size of the hash table.Hierarchical Hashingcan incur no extra write amplification to NVM when resolving hash collisions. Additionally, it can directly address all cells when resizing the hash table, thereby avoiding the additional storage overhead caused by non-addressable linked lists. Furthermore, the request performance can be improved as all cells of the hash table are addressable when resizing to resolve hash collisions. The experimental results demonstrate thatHierarchical Hashingbrings no extra write amplification to NVM and achieves nearly 90% space utilization and high request performance while providing 99% memory utilization, compared with existing representative hashing methods.
Jinquan Wang, Zhisheng Huo, Limin Xiao 0001, Jinqian Yang, Jiantong Huo, Minyi Guo
IEEE Trans. Computers2
2024 Research on performance optimization of virtual data space across WAN
Jiantong Huo, Zhisheng Huo, Limin Xiao 0002, Zhenxue He
Frontiers Comput. Sci.2
2023 Research on key technologies of edge cache in virtual data space across WAN
Jiantong Huo, Yaowen Xu, Zhisheng Huo, Limin Xiao 0002, Zhenxue He
Frontiers Comput. Sci.3
2023 A high-bandwidth and low-cost data processing approach with heterogeneous storage architectures
Bing Wei 0002, Limin Xiao 0001, Wei Wei 0006, Baicheng Yan, Zhisheng Huo
Pers. Ubiquitous Comput.6
2022 A self-tuning client-side metadata prefetching scheme for wide area network file systems
Bing Wei 0002, Limin Xiao 0001, Guangjun Qin, Jinbin Zhu, Baicheng Yan, Chaobo Wang, Zhisheng Huo
Sci. China Inf. Sci.8
2021 Fine-grained management of I/O optimizations based on workload characteristics
Bing Wei 0002, Limin Xiao 0001, Bingyu Zhou, Guangjun Qin, Baicheng Yan, Zhisheng Huo
Frontiers Comput. Sci.6
2021 Delay optimization for ternary fixed polarity Reed-Muller circuits based on multilevel adaptive quantum genetic algorithm
abstract
Delay optimization has now emerged as an important optimization goal in logic synthesis. The delay optimization for ternary fixed polarity Reed–Muller (FPRM) circuits aims to find a ternary FPRM circuit with a minimum delay. Because the delay optimization for ternary FPRM circuits is a combinatorial optimization problem, in this paper, we first propose a multilevel adaptive quantum genetic algorithm (MAQGA), which divides individuals into three-level populations: high-level population, intermediate-level population, and low-level population and uses the proposed ternary quantum rotation gate, proposed ternary quantum correction gate, and proposed multi-operator adaptive mutation mechanism to make the three-level populations evolve. Moreover, based on the proposed delay decomposition strategy, we propose a delay optimization approach (DOA) for ternary FPRM circuits under the unit delay model, which searches for a ternary FPRM circuit with a minimum delay using the MAQGA. Experimental results demonstrated the effectiveness and superiority of the DOA in optimizing the delay of ternary FPRM circuits.
Zhenxue He, Zhisheng Huo, Limin Xiao 0002, Xiang Wang 0006
Int. J. Intell. Syst.4
2020 Incremental Throughput Allocation of Heterogeneous Storage With No Disruptions in Dynamic Setting
abstract
Solid-state drives (SSDs) have been added into storage systems for improving their performance, which will bring the heterogeneity into the storage medium. The throughput is one of the essential resources in heterogeneous storage systems, and how to allocate the throughput plays a crucial role in user performance. There are many types of research on the throughput allocation of heterogeneous storage systems. However, the throughput allocation of heterogeneous storage is facing new challenges in a dynamic setting, where users are not present in the system simultaneously, and enter the system dynamically. Drawing on economic gametheory, researchers have proposed many methods to tackle dynamic throughput allocation issues for heterogeneous storages, cross out enjoying Sharing Incentive (SI), Envy Freeness (EF), and Pareto Optimality (PO). However, they either relax constraints of fairness property to cause the allocation with weak fairness or interrupt some users present in the system to give up a piece of their allocations for new users entering the system, which will degrade these donors' performance. Moreover, all of existing methods will cause lower resource utilization due to constraints of users' dominant share equality. In this article, we propose a dynamic throughout allocation method based on gradual increase (DAGI), which can adapt to various workloads to make a fair allocation with a maximum resource utilization. Without relaxing constraints of fairness properties, when new users enter the system, DAGI can make a dynamic allocation with strong fairness by appropriately postponing the allocation of surplus throughputs, so this can provide an opportunity that DAGI can guarantee the final allocation with strong fairness when allocating remaining throughputs after all users are present in the system. Meanwhile, DAGI can gradually increase user allocation without reduction, which will not interrupt any users present in the system. Furthermore, DAGI can conduct a dynamic throughput allocation based on users' local bottleneck resources, which can adapt to various workloads of users to improve resource utilization. Extensive experiments are conducted to prove the effectiveness of DAGI. The experimental results show that DAGI can achieve higher resource utilization and performance than existing methods, and can satisfy desirable game-theoretic properties with guaranteeing the strong fairness. In addition, DAGI gradually increases the allocation of each user without interrupting any user to reduce its allocation to degrade its performance.
Zhisheng Huo, Limin Xiao 0001, Minyi Guo, Xiaoling Rong
IEEE Trans. Computers1
2019 I/O Optimizations Based on Workload Characteristics for Parallel File Systems
Bing Wei 0002, Limin Xiao 0001, Bingyu Zhou, Guangjun Qin, Baicheng Yan, Zhisheng Huo
NPC6
2019 EDOA: an efficient delay optimization approach for mixed-polarity Reed-Muller logic circuits under the unit delay model
Zhenxue He, Limin Xiao 0002, Fei Gu 0001, Zhisheng Huo, Mingfa Zhu, Longbing Zhang, Rui Liu 0007, Xiang Wang 0006
Frontiers Comput. Sci.5
2019 TACD: A throughput allocation method based on variant of Cobb-Douglas for hybrid storage system
Zhisheng Huo, Minyi Guo, Zhenxue He, Xiaoling Rong, Bing Wei 0002
J. Parallel Distributed Comput.1
2017 An Efficient Polarity Optimization Approach for Fixed Polarity Reed-Muller Logic Circuits Based on Novel Binary Differential Evolution Algorithm
Zhenxue He, Guangjun Qin, Limin Xiao 0002, Fei Gu 0001, Zhisheng Huo, Haitao Wang 0017, Longbing Zhang, Jianbin Liu, Xiang Wang 0006
NPC5
2017 Balancing Global and Local Fairness Allocation Model in Heterogeneous Data Center
Bingyu Zhou, Guangjun Qin, Limin Xiao 0002, Zhisheng Huo, Jiulong Chang, Haitao Wang 0017, Zipeng Wei
NPC4
2017 An efficient and fast polarity optimization approach for mixed polarity Reed-Muller logic circuits
Zhenxue He, Limin Xiao 0002, Fei Gu 0001, Tongsheng Xia, Shubin Su, Zhisheng Huo, Longbing Zhang, Xiang Wang 0006
Frontiers Comput. Sci.6
2017 A Power and Area Optimization Approach of Mixed Polarity Reed-Muller Expression for Incompletely Specified Boolean Functions
Zhenxue He, Limin Xiao 0002, Fei Gu 0001, Zhisheng Huo, Guangjun Qin, Mingfa Zhu, Longbing Zhang, Rui Liu 0007, Xiang Wang 0006
J. Comput. Sci. Technol.5
2016 EMA-FPRMs: An efficient minimization algorithm for fixed polarity Reed-Muller expressions
abstract
Fixed polarity Reed-Muller expressions (FPRMs) are well-suited for many practical applications due to they have many excellent properties. In order to obtain an optimal FPRM with fewest product terms, we propose an efficient minimization algorithm (EMA-FPRMs) for FPRMs. The main idea behind the EMA-FPRMs is that, firstly, the incompletely specified Boolean function is transformed into the zero polarity incompletely specified fixed polarity RM expression (ISFPRM) by using the proposed ISFPRM acquisition algorithm; secondly, the polarity and allocation of don't care terms of ISFPRM is encoded as chromosome; lastly, the optimal FPRM with fewest product terms is obtained by using genetic algorithm (GA), in which the FPRM that corresponds to the given chromosome is obtained by using the proposed chromosome conversion algorithm. The experimental results on MCNC benchmark circuits show that compared with the traditional polarity optimization approach which neglects the don't care terms, the EMA-FPRMs is highly effective in minimizing the number of product terms of FPRMs. Moreover, the EMA-FPRMs is faster than the GA based minimization algorithm which also considers the don't care terms.
Zhenxue He, Limin Xiao 0002, Longbing Zhang, Fei Gu 0001, Zhisheng Huo, Mingfa Zhu, Rui Liu 0007, Xiang Wang 0006
FPT5
2016 MBFS: a parallel metadata search method based on Bloomfilters using MapReduce for large-scale file systems
Zhisheng Huo, Qiaoling Zhong, Shupan Li, Shouxin Wang, Lihong Fu
J. Supercomput.1
2015 A Metadata Cooperative Caching Architecture Based on SSD and DRAM for File Systems
Zhisheng Huo, Qiaoling Zhong, Shupan Li, Shouxin Wang, Lihong Fu
ICA3PP (2)1