A cryogenic complementary metal-oxide semiconductor (cryo-CMOS) ultra-high-frequency (UHF) analog filter designed for enabling scalable quantum control interfaces is presented in this work. Effective filtering at both analog-to-digital and digital-to-analog conversion stages is critical to maintain signal integrity and achieve high-fidelity qubit control and readout. The proposed filter employs a differential flipped-voltage-follower-based topology, facilitating compact single-branch design, high linearity, and low power consumption. An on-chip buffer stage and a de-embedding technique for precise chip measurements are also presented. The filter is designed using the GlobalFoundries 22nm fully depleted silicon-on-insulator (FD-SOI) technology, leveraging a low-voltage operation of 0.8 V, facilitating low power consumption. A key advantage of using FD-SOI technology for enabling cryogenic quantum computing hardware is the additional degree of freedom provided by the available back-gate transistor connection through which the – increased by the cryogenic (4 K) environment – threshold voltage can be restored. The filter's performance is validated through post-layout simulations, demonstrating improved performance compared to the state-of-the-art literature regarding bandwidth, linearity, and power consumption.

In the realm of neurostimulation, magnetic techniques have emerged as a promising modality for both fundamental neuroscience investigations and the clinical management of neurological disorders, potentially surpassing the limitations associated with conventional electrical stimulation. This study investigated the feasibility of spiral µ-coils for magnetic neurostimulation, employing both computational modeling and experimental validation. Computational modeling demonstrated that varying current amplitudes (1-5 A) across the tested frequency range resulted in average magnetic (B) flux densities ranging from 8.41 to 42.05 mT, sufficient to achieve a neurostimulation depth of approximately 2 cm within the model. Experimental optimisation identified a laser cutting power of 2.6 W. Corresponding measurements of the B-field revealed a spatial gradient, with values ranging from 1.72 µT at the coil's center to 772.26 nT at a radial distance of 25 mm. These results indicate the potential of magnetic neurostimulation for modulating neural activity in subcortical brain regions.

This brief presents a new method to characterize the linearity of on-chip filters with accurate characterization of the filter’s transfer function (TF) in both its bandpass and stopband. Unlike conventional methods, this approach uses only one buffer, simplifying the design and improving accuracy. The filter and buffer are designed using GlobalFoundries (GF) 22-nm FDX technology, incorporating a back-gate biasing tuning mechanism in the buffer design that aims to maintain the performance of the buffer under process variation. The postlayout simulations demonstrate that the new method achieves a filter linearity of$\text {IIP3}=10.46~\text {dBm}$, with an accuracy of 99.4% compared to the standalone filter’s linearity. Similar consistency is observed across process corners.

This work presents two 4-bit resistor-string digital-to-analog converters (R-DAC) designed in 22nm FDSOI technology. Both DACs are connected to a shared resistor string to make the final layout more compact. The small on-resistance of the Transmission-Gate (TG) switches designed in the FDSOI node yields a low Internal non-linearity (INL) and Differential non-linearity (DNL) in the DACs output. The effect of the temperature variations on the linearity performance of the DACs is also studied. It is shown that the temperature gradients can be compensated for by equally distributing the switches on the layout area. Post-layout simulations show an approximately fixed INL and DNL of, respectively, 0. 17LSB and 0. 1LSB over a wide temperature range from -40°C to $125^{0} C$. Two R-DACs dissipate the static/dynamic power of 0. 12/0.155mW with the layout size of only 70 $\mu m^{2}$, showing a high performance for two 4-bit DACs.

The inefficiencies of von-Neumann computing architectures in performing high-level machine learning and neuromorphic operations have led to the need for new computational systems such as oscillatory neural networks, that are designed using emerging technologies. The frequency dynamics of Ferroelectric field-effect transistor (FeFET)-based coupled oscillator neurons, as integral parts of these novel computational networks are investigated in this paper. The concept of time to frequency modulation is also introduced which can be used to distinguish dynamical changes in the incoming signals. Simulation results show a significant reduction in power consumption with approximately 9 μW for each oscillator neuron. This is significant improvement over results reported for spin-torque and metal-insulator-migration oxide-based coupled-oscillators. Integrability with CMOS technology in conjunction with lower power consumption and simpler topologies make FeFET devices promising candidates for the next generation of neuromorphic computing platforms, and particularly for image, video, and audio processing tasks.

Degradation of power amplifier (PA), being a main part of a transceiver chain, affects the overall performance of a transceiver. This article reports, for the first time, an analytical reliability model of the hot-carrier injection (HCI) induced degradation in silicon-based PAs. HCI causes substrate current which is used to develop the proposed model. This model fits very well the simulation results of RelXpert, which is a well-established reliability simulation tool. This model predicts circuit degradation as a function of conduction angle and is valid for the different classes of PAs. With this model, a new approach for “reliability aware design” for PA design is developed and a tradeoff between PA performance and reliability is introduced.