The adoption of small geometries and multi-level cell (MLC) technologies significantly expands the capacity and drops the price of flash memory, which, at the same time, noticeably degrades the performance and reliability of the devices. As incremental-step pulse programming (ISPP) scheme is used to increase the programming accuracy for MLC cells, there is a trade-off between the SSD write performance and raw storage reliability. What's more, ECC is widely used in SSDs to provide error-tolerance ability. Therefore, if we could use stronger ECC to increase error correction strength, a low-cost write with coarser step sizes could be applied in the ISPP scheme to promote the write performance. However, stronger ECC scheme may hurt the read performance due to the increased decoding complexity and latency. In this paper, we propose a workload-aware differentiated ECC scheme to improve the SSD write performance without sacrificing the read performance. The main idea is to dynamically classify the logical pages into three categories: write-only, readonly, and overlapped part. For write-only logical pages, low-cost write with strong ECC scheme will be applied to increase the write performance. For write logical pages in the overlapped part, the low-cost writes with strong ECC will be selectively used based on their relative write and read hotness. While for any read logical pages encoded with a stronger ECC, we will rewrite them with the normal-cost write and ECC scheme if their hotness exceed a pre-defined threshold. The evaluation results show that our workload-aware differentiated ECC scheme could reduce the write and read response times by 48% and 11% on average, respectively. Even compared with the latest previous work, our workload-aware design can still gain about 4% write performance and 11% read performance improvements.

Flash-based SSDs are widely used as storage caches, which can benefit from both the higher performance of SSDs and lower price of disks. Unfortunately, issues of reliability and lifetime limit the use of flash-based cache. One way to solve this problem is to use the flash memory as read cache and use other devices like nonvolatile memory for write buffering. In this paper, we propose a new flash-aware read cache design, which leverages out-of-place update property of SSDs to improve both cache hit ratio and lifetime. Due to the out-of-place update property, when a cache entry is evicted from the flash cache, the eviction only removes the metadata, while the real data is still accessible and resides in the physical flash page until the whole flash block being erased. The main idea of our flash-aware cache is to reuse these evicted but still available data, when a request for the previously evicted data page arrives, instead of accessing underlying storage to fetch the data and rewriting it into fash cache, our design just needs to revive the evicted data. To evaluate the benefits of flash-aware cache design, we implemented the normal LRU, normal ARC, flash-aware LRU (FLRU), and flashaware ARC (FARC) cache algorithms on the Disksim simulator with SSD extension. Our simulation results demonstrate that our flashaware cache can improve the cache hit ratio by up to 28 percent, reduce the average response time by up to 40 percent with higher performance stability, and alleviate the lifetime limitation of flash cache by reducing the erase count by up to more than 70 percent. Besides of the flash-aware design, we also propose a new zero-migration garbage collection scheme to further extend the lifetime of flash cache. Our experiments show that the combination of our flash-aware cache design and the zero-migration garbage collection scheme reduces the erase count by up to nearly 90 percent.

Flash-based SSDs are widely used as storage caches, which can benefit from both the higher performance of SSDs and lower price of disks. Unfortunately, issues of reliability and limited lifetime limit the use of Flash-based cache. One way to solve this problem is to use the flash memory as read cache and use other devices like nonvolatile memory for write buffering. In this paper, we propose a new flash-aware read cache architecture, which leverages out-of-place update property of flash memory to improve both cache hit ratio and lifetime. Due to the out-of-place update property, when a cache entry is evicted from the flash cache, the eviction only removes the metadata, while the real data is still accessible and resides in the physical flash page until the whole flash block being erased. The main idea of our flash-aware cache is to reuse these evicted but still available data, when a request for the previously evicted data arrives, instead of accessing underlying storage to fetch the data and rewriting it into flash cache, we just need to revive the evicted data. To evaluate the benefits of flash-aware cache design, we implemented the normal LRU and flash-aware LRU (FLRU) cache algorithms on the Disksim simulator with an SSD extension. Our simulation results demonstrate that our flash-aware cache can improve the cache hit ratio by up to 28% and alleviate the lifetime limitation of flash cache by reducing the erase count by up to 70%.