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Stephen Pruett

dblp:172/4250 · DBLP profile ↗
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2ranked-venue papers
1as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Processor architecture and microarchitecture · 96% Hardware accelerators and domain-specific architectures · 4%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
branch prediction
0.922021
Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches · MICRO 2021
BranchNet: A Convolutional Neural Network to Predict Hard-To-Predict Branches · MICRO 2020
Processor architecture and microarchitecture › front-end
instruction supply
0.512021
Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches · MICRO 2021
Processor architecture and microarchitecture › latency hiding
runahead execution
0.512021
Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches · MICRO 2021
Processor architecture and microarchitecture
speculative execution
0.512021
Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches · MICRO 2021
Processor architecture and microarchitecture › branch prediction
neural branch prediction
0.412020
BranchNet: A Convolutional Neural Network to Predict Hard-To-Predict Branches · MICRO 2020
Processor architecture and microarchitecture
instruction-level parallelism
0.112021
Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches · MICRO 2021
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.112020
BranchNet: A Convolutional Neural Network to Predict Hard-To-Predict Branches · MICRO 2020

Methods — techniques the papers use, named apart from their topics

precomputation · 0.5hardware-only speculation · 0.5hybrid prediction · 0.4convolutional neural network · 0.4compile-time training · 0.4
YearPublicationVenuePosition
2021 Branch Runahead: An Alternative to Branch Prediction for Impossible to Predict Branches
abstract
High performance microprocessors require high levels of instruction supply. Branch prediction has been the most important driver of this for nearly 30 years. Unfortunately, modern predictors are increasingly bottlenecked by hard-to-predict data-dependent branches that fundamentally cannot be predicted via a history based approach. Pre-computation of branch instructions has been suggested as a solution, but such schemes require a careful trade-off between timeliness and complexity. This paper introduces Branch Runahead: a low-cost, hardware-only solution that achieves high accuracy while only performing lightweight pre-computation. The result: a reduction in branch MPKI of 47.5% and an average improvement in IPC of 16.9%.
Stephen Pruett, Yale N. Patt
MICRO1
2020 BranchNet: A Convolutional Neural Network to Predict Hard-To-Predict Branches
abstract
The state-of-the-art branch predictor, TAGE, remains inefficient at identifying correlated branches deep in a noisy global branch history. We argue this inefficiency is a fundamental limitation of runtime branch prediction and not a coincidental artifact due to the design of TAGE. To further improve branch prediction, we need to relax the constraint of runtime only training and adopt more sophisticated prediction mechanisms. To this end, Tarsa et al. proposed using convolutional neural networks (CNNs) that are trained at compile-time to accurately predict branches that TAGE cannot. Given enough profiling coverage, CNNs learn input-independent branch correlations that can accurately predict branches when running a program with unseen inputs. We build on their work and introduce BranchNet, a CNN with a practical on-chip inference engine tailored to the needs of branch prediction. At runtime, BranchNet predicts a few hard-to-predict branches, while TAGE-SC-L predicts the remaining branches. This hybrid approach reduces the MPKI of SPEC2017 Integer benchmarks by 7.6% (and up to 15.7%) when compared to a very large (impractical) MTAGE-SC baseline, demonstrating a fundamental advantage in the prediction capabilities of BranchNet compared to TAGE-like predictors. We also propose a practical resource-constrained variant of BranchNet that improves the MPKI by 9.6% (and up to 17.7%) compared to a 64KB TAGE-SC-L without increasing the prediction latency.
Siavash Zangeneh, Stephen Pruett, Sangkug Lym, Yale N. Patt
MICRO2