Protecting data and hardware is vital, driving the adoption of Physically Unclonable Functions (PUFs) for generating unique circuit signatures. This paper introduces a fault-tolerant system featuring a ring-oscillator (RO) based PUF, utilizing a reversible logic (RL) design. The proposed system comprises various sub-systems such as Fault-Tolerant RL-based inverter design, Reversible-Logic designing, Fault-Detection module, Fault-free path selection module, and the Reversible RO-PUF module. The proposed design is implemented on a Basys-3 FPGA board for calculating various PUF parameters. It is observed that the uniqueness, uniformity, and bit-aliasing of the proposed design at 27°C are 49.40%, 51.20%, and 48.30%, respectively. Further, bit-error-rate (BER), reliability, and key error rate (KER) are determined at three different temperatures, and the best results obtained are 0.003%, 99.7%, and 0.092 at 40°C, respectively. Compared to conventional PUFs, the proposed design showcases higher reliability (0.002% to 0.11%) and significantly reduced BER and KER ($1.67\times $to$22.67\times $, and$1.6\times $to$8.02\times $respectively). The proposed design also passed 15 NIST tests against conventional RO-PUF, which could pass only 11 NIST tests. We have also tested the resilience of different PUF designs against three machine-learning models with the best accuracy of 58.9% against the Logistic Regression model.

Extremely energetic particles prevalent in the nuclear environment make memory cells prone to soft errors. Also, attackers extract secret data of SRAM cells via side-channel attacks (SCAs), and leakage power analysis attacks (LPAs) are a serious threat to security systems. This research indicates an extremely effective radiation-hardened and LPA-resilient (RHLR12T) SRAM cell that is both radiation resistant by design for nuclear applications and LPA-resilient. It offers better speed, enhanced writing stability and higher overlap percentage compared to other considered SRAM cells, such as 6T, Quatro, We-Quatro, and RHMD10T, utilizing 45nm CMOS technology at the supply voltage of 1.0V and 27-C operating temperature. The proposed cell gives 1.141× higher write stability, 1.55× lower write access time, 1.11× increased critical charge and 1.51× better overlap percentage than RHMD10T SRAM cell.

The impact of high-energy particles in space like cosmic rays and alpha particles flips the stored data in an SRAM cell. This paper proposes a highly reliable soft error immune with enhanced critical charge 14T (SIC14T) SRAM cell that is radiation-hardened by design and has an increased critical charge that can withstand both single-event upsets (SEU) and single-event multi-node upsets (SEMNU). We compare the performance of the proposed cell with that of other considered SRAM cells, such as the SRRD12T, RSP14T, SEA14T, and 6T SRAM cell which were simulated in 45-nm CMOS technology in Cadence Virtuoso with a supply voltage of 1V and 27°C operating temperature. Both SEU and SEMNU caused at the storage node of SIC14T are successfully recovered. The proposed SRAM cell has 1.02×, 0.6×, 0.72×, and 4.64× better write stability, read access time, leakage power, and critical charge than the SRRD12T with 1.68× area overhead.

In this paper, a new XOR gate is discussed in quantum-dot cellular automata (QCA). The proposed gate is a single layer structure with no crossovers, and has been designed with redundant cells to increase the amplitude of the output signal and to improve the fault tolerance and reliability of the circuit. Based on the performance comparison, the investigated XOR gate has very high fault tolerance to single-cell addition and single-cell omission defects, thereby making them suitable candidates for designing reliable QCA based digital circuits.

Soft error is one of the major reliability issue with technology scaling. In this work, we propose a radiation hardened voltage bootstrapped schmitt trigger (VB-ST) latch. To evaluate the circuit radiation resilience, we calculated the critical charge under the PVT variations at the most sensitive node and observed that the proposed latch has the highest critical charge and the lowest soft error rate ratio when compared to existing latches. We analyzed the impact of process variations on our design and observed that the VB-ST latch has 0.42x less critical voltage variability as compared to ST latch. Further, dynamic power and propagation delay are examined for various supply voltages, and we observed that the VB-ST latch has the lowest power consumption and delay propagation when compared to the other considered latches. For the validation of the proposed latch, a charge to power-delay-area product ratio (QPAR) is calculated and we clearly observed that the proposed VB-ST based latch significantly outperforms the performance of existing designs.

Aging and soft errors are the two most critical reliability issues for nanoscale CMOS circuits. The soft error becomes more severe if the circuit performance degraded with the aging. In this paper, we address the issue of analyzing the effects of Negative Bias Temperature Instability (NBTI) mechanisms on Integrated Circuit's (ICs') soft error susceptibility. We first analyzed the critical charge sensitivity of two-input NAND gate for various operating temperatures with three years of stress. Results show that the critical charge decreases with the temperature and has the maximum degradation of 19.98% if the input AB is at 01 logic compare to 12.06%, 16.8%, and 11.15% for 00, 10, and 11. Further, we validated the results with c17 from ISCAS'85 benchmark suite to estimate the soft error. The critical charge at the sensitive node of the c17 circuit is decreased by 9.87% for the worst case input pattern 00010. Thus thorough investigation of the critical charge provides a measure for the soft error susceptibility with the NBTI effect on ICs.