This article presents the HAS-16T static random access memory (SRAM) cell, a novel 16-transistor design implemented in 45 nm CMOS technology to achieve robust security against side-channel attacks (SCAs) and fault injection attacks (FIAs). The cell integrates sleep transistors, loop-cut mechanisms, prewrite conditioning, and an inverter feedback loop to mitigate leakage power analysis (LPA), timing analysis attacks (TAAs), and FIAs. A comprehensive security measure, based on Monte Carlo simulations (1000 samples, 1 V,$27~^{\circ } $C), quantifies resistance through histogram overlap and failure probability, yielding a total security matrix (SMTotal) of 98.68%, the highest among evaluated cells (e.g., 6T: 38.37%, EQ-14T: 68.91%). Simulations in the Cadence design environment reveal the HAS-16T’s second-highest static noise margin (SNM), moderate read/write delays, second-lowest write dynamic power, and second-highest leakage power, reflecting a balanced tradeoff for security-critical applications. Compared to conventional and secure SRAM designs, the HAS-16T offers unparalleled protection, making it ideal for cryptographic and embedded systems. Future work includes area optimization and scalability to advanced process nodes.

This addresses the error in [1]. Table I Column 1 wrong citation: 8T [14]ST-12T [15]LC-7T [16]QUCC-12T [17]RHBD-14T [18]SEUH-12T [19]RH-12T [20]RH-14T [21]EQ-14T [22].

Cryptography is essential to ensure data security in embedded devices that handle sensitive data. SRAM boosts overall performance by temporarily storing cryptographic keys. However, attackers can use side-channel, such as Power Analysis, to exploit power consumption patterns and extract secret keys. Once a key is compromised, encrypted data becomes vulnerable. There are many secure SRAM cell designs available in the literature, but they often degrade other performance parameters. This article presents a novel 10-T SRAM cell design that provides protection against power analysis side-channel attacks (SCA) across all three cell operations, while also maintaining the performance of other key parameters. Monte Carlo simulations were conducted on 1,000 samples each for case when BL = Q and BL ≠ Q during reading, writing, and holding data, using Cadence Virtuoso with a 45-nm technology node at 1V/270°C. Based on these simulations, the mean power difference was evaluated. The proposed P-10T SRAM cell exhibits a 0% mean power difference in all three modes of operation, demonstrating complete resilience to power analysis SCA. The design achieves 84.87% reliability with hold stability, read stability, and write ability values of 429 mV, 242 mV, and 250 mV, respectively. Furthermore, the write power dissipation of P-10T cell is 57.44 μW, which is 1.80 × lower than the power consumed by the conventional 6T cell.