This paper presents a receiver design that has a summer integrated latch in a decision feedback equalizer (DFE) for wireline chip-to-chip communication. The proposed DFE cancels the first post-cursor by modulating the rising edge of the clock of the latch. This leads to a reduced clock-to-Q delay of the latch along with the improvement in loop delay for the first tap of the DFE. The proposed 1-tap DFE using the clock-based summer-latch (CSL) along with a single-stage continuous time linear equalizer (CTLE) has been implemented in the front end of the receiver and fabricated in TSMC 65-nm CMOS technology. The prototype has been measured at a data rate of 9 Gb/s for a FR4 channel having a loss of 14.75 dB at Nyquist frequency. The total power consumption of the implemented receiver is 3.7 mW with an energy efficiency of 0.41 pJ/b for a BER$10^{-12}$. The complete 1-tap quarter rate DFE occupies an core area of 0.00525 mm2.

This paper presents a full-duplex simultaneous bidirectional (FD-SBD) signaling transceiver designed to overcome the switching supply noise (SSN). The signal-to-noise ratio (SNR) is impacted mainly by transmitter echo signal, inter-symbol interference (ISI), SSN, etc. This paper primarily focuses on comparing the impact of SSN on the transceiver. In general, the voltage mode (VM) transmitter injects more SSN compared to the current mode (CM) transmitter. To address this, the proposed architecture combines voltage mode source series terminated (VM-SST) and current mode logic (CML) transmitters to improve SNR by mitigating the effect of SSN. In addition, this paper proposed a passive R-Gm hybrid for linear and energy-efficient subtraction of the transmitted signal and extracting the received signal. Implemented in TSMC-65 nm CMOS technology for a link with 3 dB insertion loss at 5 GHz Nyquist frequency, the simulated results of the proposed architecture improve the eyeopening by 30% at 10+10 Gb/s SBD data rate.

This paper presents a current mode (CM) replica driverless full-duplex simultaneous bidirectional (FD-SBD) signaling transceiver for chip-to-chip interconnect. For FD-SBD signaling a hybrid architecture is used to extract the received signal from the channel by canceling the transmitted signal. However, the pin package parasitics at the interface increases the near-end reflection and increases the cancellation error which reduces the received signal eye opening. Reducing the cancellation error by using filters increases the power consumption along with the complexity. In the case of single-ended full-duplex signaling with dedicated wires for transmitting and receiving, the received signal eye opening is affected significantly by the cross-talk and power supply noise. Therefore, in this work a hybrid of differential and common mode signaling is used to reduce the cancellation error and common-mode noise to increase the data rate. The proposed transceiver does not require an additional replica driver to retrive the received signal unlike conventional transceivers. The architecture is designed using 65 nm CMOS technology for a 7.5-inch channel with 6.46 dB insertion loss at 5 GHz Nyquist frequency. An aggregate full-duplex data rate of 30 Gb/s with an energy efficiency of 0.43 pJ/b is achieved in this work.

This paper presents a single-ended voltage-mode (VM) simultaneous bidirectional (SBD) transceiver for chip-to-chip interconnects. A hybrid network in the receive path cancels the transmitted signal to extract the received signal enabling SBD signaling. The conventional source-series terminated (SST) and trans-impedance amplifier (TIA)-based transmitters used in the SBD signaling transceivers consume high power to minimize output impedance variation. The proposed design minimize this variation with low power consumption, thereby leading to a low-power transceiver. In addition, the power consumption while incorporating feed-forward equalizer (FFE) is reduced by using current-mode implementation in the proposed transceiver. Implemented using TSMC PDK in 65 nm technology, the simulation results gives an energy efficiency of 0.35 pJ/b at 20 Gb/s SBD data-rate.

This paper presents an energy-efficient, half-rate charge-steering logic (HR-CSL) based echo cancellation hybrid (ECH) circuit topology for full-duplex(FD) signaling across chip-to-chip interconnects. The proposed charge-steering logic (CSL) based hybrid has much lower power consumption compared to conventional current-mode logic (CML) and voltage-mode logic (VML) based hybrid implementations, thanks to the discrete nature of CSL hybrid topology avoiding direct current path between$V_{DD}$and ground. The prototype test chip design of the proposed hybrid circuit topology has been fabricated in 65 nm CMOS for a 20 cm FR4 PCB chip-to-chip interconnect with a supply voltage of 1.2 V. The measurement performance of the HR-CSL based hybrid circuit achieves 8 Gb/s FD operation at a power consumption of only 0.15 mW with an energy efficiency of 0.0375 pJ/bit. The measurement results show that the proposed hybrid circuit has a differential received signal voltage swing of 110 mV at 8 Gb/s data rate with a timing jitter of 20 ps. The proposed hybrid has a clock phase margin of 25% UI at bit-error-rate (BER) less than$10^{-12}$. The active area of the hybrid is 0.0007 mm2.

This paper presents an energy-efficient full-duplex simultaneous bidirectional (FD-SBD) signaling transceiver to double the aggregate data transfer per pin for serial links. For achieving FD-SBD signaling, the transceiver employs a resistor-transconductance (R-Gm) hybrid-based subtractor to enable concurrent transmission and reception of non-return to zero (NRZ) data stream on a single differential channel. The transmitter of a conventional current-mode R-Gm hybrid transmits through a split termination, which effectively reduces the impedance at the transmitting node and increases the power consumed by the transmitter by almost two times compared to the conventional current-mode logic (CML) transmitter. In this work, we have proposed a current-sharing topology by reusing the same transmitter current in both transceivers so that the power consumed by the transmitters is reduced by$2\times $. A prototype of the proposed transceiver has been implemented in 65 nm CMOS technology for full-duplex signaling across a short FR4 link with a 2.5 dB insertion loss at Nyquist frequency. Measured results give an energy efficiency of 1.7 pJ/b at an aggregate data rate of 8.6 Gb/s with a bit error rate (BER)$\lt 10^{-12}$.

In this paper, a current mode (CM) full-duplex simultaneous bidirectional (FD-SBD) transceiver has been presented for chip-to-chip interconnect. To enable simultaneous bidirectional communication, the transceiver incorporates a hybrid network in the receive path, which not only eliminates the transmitted signal but also its reflections due to channel imperfections. A front-end programmable active delay line (PADL) and an approximate impedance matching network (IMN) at replica end forms the hybrid network to move and reduce the echo from received signal (RX) sampling point. The architecture has been implemented using 65 nm CMOS technology for a short channel with 4.375 dB insertion loss at 7.5 GHz. Post-layout simulation of the bidirectional transceiver with the link, gives an energy efficiency of 1.8 pJ/b, at aggregate data rate of 26 Gb/s.

In this paper, an energy efficient current-mode hybrid circuit topology for echo-cancellation is proposed for full-duplex signalling over chip-to-chip interconnects. Conventional full-duplex transceivers consists of three transcondutors, namely, for transmitting the outbound signal, for replica generation and for cancellation or subtraction, leading to an increase in the power consumption. However, the proposed hybrid circuit topology consists of only two transconductors, transmitter and replica generator. The separation of the inbound signal from the signal on the line is achieved using a simple resistor, thereby eliminating the need of additional transconductor for subtraction. This makes the proposed hybrid an attractive choice for realizing power efficient full-duplex transceiver compared to the existing transceiver with current-mode and voltage-mode hybrid circuit topologies. The proposed hybrid is implemented in 65 nm CMOS technology with a supply voltage of 1.2 V. The post-layout simulation including the package parasitic has a differential received signal voltage swing of 85 mV at 10 Gb/s data rate over a 20-cm FR4 PCB trace. The total power consumption of the hybrid is 0.29 mW and the corresponding energy efficiency is 0.057 pJ/bit. The layout of the hybrid occupies an area of 0.00025 mm2.

In this paper, a low-power half-rate charge-steering echo cancellation hybrid circuit topology is proposed for full-duplex signaling over chip-to-chip interconnects. The proposed half-rate charge-steering hybrid topology has a very low power consumption compared to traditional current-mode and voltage-mode hybrid circuit topology implementations, thanks to the discrete nature of charge-steering hybrid topology avoiding direct current path between VDDand ground. The half-rate hybrid circuit topology has been implemented in 65 nm CMOS technology with a supply voltage of 1.2 V. The post-layout performance of the half-rate charge-steering hybrid including package parasitic has a differential received signal voltage swing of 0.8 V at 10 Gb/s data rate with a timing jitter of 10 ps over a FR4 PCB interconnect of length 20 cm. The total power consumption of the half-rate charge-steering hybrid is only 0.16 mW and its energy efficiency is 0.032 pJ/bit. The layout of the hybrid occupies an area of 0.0007 mm2.

This paper presents all-digital calibration algorithms for correcting static non-linearities in an ADC. A bit-by-bit (BB) calibration is proposed as an alternative to the existing radix calibration. The proposed calibration algorithm is initially demonstrated using a non-uniform ADC model generated in Matlab. A hybrid radix/bit-by-bit calibration is also developed to reduce the computational complexity of BB calibration. The calibration algorithms are then applied to measurement data from two different ADCs: a 6-bit folding-flash; and a 10-bit dual-split capacitor (DSC)-DAC SAR ADC. In both ADC architectures, the BB and hybrid calibrations outperform radix calibration. The BB calibration improved the SNDR and SFDR of the folding-flash ADC from 29.5 dB to 31.9 dB and 33.3 dB to 43.6 dB, respectively. Likewise, after applying the hybrid calibration on the DSC-DAC SAR ADC, the SNDR and SFDR improved from 31.8 dB to 47 dB and 33.6 dB to 58.9 dB, respectively. The hybrid calibration achieves performance similar to that of BB calibration while demonstrating a significant reduction in computational complexity.

For serial wireline communication beyond 56 Gb/s, bandwidth-efficient modulation is needed. Four-level pulse amplitude modulation (4-PAM) has become the standard technique at 56-64 and 112 Gb/s. However, whereas decision feedback equalization (DFE) with 5 taps or more was common for 2-PAM links at lower data rates, the speculative look-ahead techniques required to satisfy a DFE's timing requirements at 56 Gb/s increase power consumption exponentially with the number of taps and the number of modulation levels. Thus, 4-PAM DFEs at 56 Gb/s are generally limited to 2 taps or fewer. This limitation, in turn, necessitates the use of long (10 taps or more) finite impulse response (FIR) feed-forward equalization (FFE) to accurately eliminate the intersymbol interference in long reach (LR) channels. Thus, LR receivers at 56-64 and 112 Gb/s comprise an analog-to-digital converter (ADC) followed by digital equalization, and the transmitters increasingly use a digital-to-analog converter (DAC) preceded by a digital filter. Discrete multitone (DMT) signalling obviates the need for a long FIR FFE and DFE, and has demonstrated better spectral efficiency than 4-PAM above 50 Gb/s. In this work, we consider the potential of DMT for wireline communication beyond 100 Gb/s. For example, a spectral efficiency of 2.5 bits/sample is achievable over an IEEE P802.3ck channel with 18 dB loss at 40 GHz, affording an aggregate data rate of 200 Gb/s at 80 GS/s with 150 fs of jitter and 1.26 mV of noise at the input to the receiver. Significant improvement in bit error rate (BER) is obtained by increasing DAC resolution to 8 bits.

This paper presents a current-mode triline ternarylevel coded differential signaling scheme for high-speed data transmission across on-chip global interconnects. An energy efficient current-mode triline transceiver pair suitable for this signaling scheme has been proposed. Compared with a voltage mode receiver with resistive termination, the proposed active terminated current-mode receiver reduces the signal current by 7.8 times and the signaling power by 2.6 times. Two data transmission schemes are proposed for using this transceiver pair. In the first scheme, two data streams are directly transmitted over the three lines link, thereby having a wire efficiency of 67%. In the second scheme, five data streams at half rate are encoded and serialized to send over the three lines, thereby having a wire efficiency of 83%. A prototype design has been implemented in a UMC 0.18-μm technology for an interconnect of length 5 mm. The measured energy efficiency of the triline transceiver in a direct transmission scheme for the data rate of 7.4 Gb/s is 0.61 pJ/bit. With the encoding scheme, the energy efficiency is 1.24 pJ/bit for a total data transmission of 9.25 Gb/s.