EDBT 2026 Demo / reviewers in the wild / expert
Racyus D. G. Pacífico
dblp:173/1217 · also Racyus Delano Garcia Pacífico
· DBLP profile ↗
4ranked-venue papers
3as first author
2since 2021 · last 2024
0000-0003-0587-6127ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 3 · 3 first-author · 2 since 2021Human-computer interaction and ubiquitous computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Reconfigurable computing and FPGAs · 77% Hardware accelerators and domain-specific architectures · 23% | |
| Computer networks
1 paper |
Software-defined and programmable networks · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Software-defined and programmable networks
programmable data plane |
0.8 | 1 | 2024 | eBPFlow: A Hardware/Software Platform to Seamlessly Offload Network Functions Leveraging eBPF · IEEE/ACM Trans. Netw. 2024 |
Reconfigurable computing and FPGAs › FPGA-based network processing
FPGA-based network acceleration |
0.8 | 1 | 2024 | eBPFlow: A Hardware/Software Platform to Seamlessly Offload Network Functions Leveraging eBPF · IEEE/ACM Trans. Netw. 2024 |
Hardware accelerators and domain-specific architectures
network function acceleration |
0.2 | 1 | 2024 | eBPFlow: A Hardware/Software Platform to Seamlessly Offload Network Functions Leveraging eBPF · IEEE/ACM Trans. Netw. 2024 |
Methods — techniques the papers use, named apart from their topics
eBPF · 1.5FPGA implementation · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | eBPFlow: A Hardware/Software Platform to Seamlessly Offload Network Functions Leveraging eBPFabstractNFV and SDN enable flexibility and programmability at the data plane. In addition, offloading packet processing to a hardware saves processing resources to compute other workloads. However, fulfilling requirements such as high throughput and low latency with a flexible and programmable data plane is challenging. This paper introduces eBPFlow, a platform for seamlessly accelerating network computation. It builds upon eBPF. eBPFlow combines flexibility and programmability in software with high performance using an FPGA. We implemented our system on the NetFPGA SUME, performing tests on a physical testbed. We built a range of NFs. Our results show that the eBPFlow supports offloading of NFs with throughput at the line rate, latency between$20~\mu \text{s}$and$40~\mu \text{s}$, communication with host, and consumption of 22 W. Moreover, eBPFlow processes 12.05 Mpps more than the kernel. eBPFlow has a throughput of 2.59 Gbps higher than the hXDP, a system similar to eBPFlow. Racyus D. G. Pacífico, Lucas Ferreira Dos Santos Duarte, Luiz Filipe M. Vieira, Barath Raghavan, José A. M. Nacif, Marcos A. M. Vieira |
IEEE/ACM Trans. Netw. | 1 |
| 2021 | Application Layer Packet Classifier in Hardware
Racyus D. G. Pacífico, Matheus S. Castanho, Luiz Filipe M. Vieira, Marcos A. M. Vieira, Lucas Ferreira Dos Santos Duarte, José A. M. Nacif |
IM | 1 |
| 2016 | Hardware Modules for Packet Interarrival Time Monitoring for Software Defined MeasurementsabstractMeasurement and tracking have crucial roles in Software-Defined Networks (SDNs). Unfortunately, most of procedures and techniques to perform measurements and monitoring tasks are implemented in software at network end-hosts. Despite the large use, a software based approach generates imprecision, high costs, and makes monitoring more difficult. In this paper, we extend OpenFlow switch to implement a measurement architecture for SDN. Our system performs measurements in a simple and scalable way without depending on end-hosts. It allows monitoring the performance at the granularity of flows. Moreover, our system also enables software-defined measurements can collect flow's statistics on the fly. We have prototyped our architecture on the NetFPGA platform and, as an initial case study, we have implemented a module to measure packet interarrival time. This module has been validated in a realistic testbed. Our results demonstrate that the proposed architecture presents a negligible difference when compared to measurements performed by software at end-hosts. Racyus D. G. Pacífico, Pablo Goulart, Alex Borges Vieira, Marcos A. M. Vieira, José A. M. Nacif |
LCN | 1 |
| 2015 | Be a simulator developer and go beyond in computing engineeringabstractThis work presents a methodology based on simulator developers to be applied in several courses as well as research activities. This proposal is also based on “The Cathedral and the Bazaar” lessons. First, good programmers know what to write, however great ones know what to rewrite. Students could learn by developing new components to be added to the current simulator. Second, any tool should be useful in the expected way, but a truly great tool lends itself to uses you never expected. The proposed simulator has been developed to teach digital circuits. However, it can be used in many other computing engineering fields. Third point is motivation, where the lessons are driven by the following principle: To solve an interesting problem, start by finding a problem that is interesting to you. Nowadays, we are surrounded by Internet of things, where the simulator engine could be connected to learn and to motivate the students. Image processing could be taught by connecting your web-cam and/or your mobile device camera to your simulator engine. Moreover, mobile phones and/or Arduino devices have a set of sensors that could be captured inside of the virtual simulator lab. Ricardo S. Ferreira 0001, José A. M. Nacif, Salles V. G. Magalhães, Thales T. de Almeida, Racyus D. G. Pacífico |
FIE | 5 |