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A. K. Kamal

dblp:173/1793 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1974
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 67% Processor architecture and microarchitecture · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
arithmetic unit
0.011974
A Generalized Pipeline Array · IEEE Trans. Computers 1974
Integrated circuit design › VLSI design
cellular array
0.011974
A Generalized Pipeline Array · IEEE Trans. Computers 1974
Integrated circuit design
digital circuit design
0.011974
A Generalized Pipeline Array · IEEE Trans. Computers 1974

Methods — techniques the papers use, named apart from their topics

iterative array design · 0.0
YearPublicationVenuePosition
1974 A Generalized Pipeline Array
abstract
A generalized pipeline cellular array has been proposed which can perform all the basic operations such as multiplication, division, squaring, and square rooting. The different modes of operation are controlled by a single control line. An expression for time delay has been obtained. Further, it has been shown that these arithmetic operations can be overlapped in the pipe in any desired sequence, and thus significant speed improvement can be achieved. The array is fully iterative and hence is suitable for large-scale integration (LSI).
A. K. Kamal, D. P. Agrawal
IEEE Trans. Computers1